<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/Documentation/gpu/amdgpu/display, branch v6.6.132</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>Documentation: Fix typos</title>
<updated>2023-08-18T17:29:03+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2023-08-14T21:28:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=d56b699d76d1b352f7a3d3a0a3e91c79b8612d94'/>
<id>d56b699d76d1b352f7a3d3a0a3e91c79b8612d94</id>
<content type='text'>
Fix typos in Documentation.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Link: https://lore.kernel.org/r/20230814212822.193684-4-helgaas@kernel.org
Signed-off-by: Jonathan Corbet &lt;corbet@lwn.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix typos in Documentation.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Link: https://lore.kernel.org/r/20230814212822.193684-4-helgaas@kernel.org
Signed-off-by: Jonathan Corbet &lt;corbet@lwn.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: add prefix to amdgpu_dm_plane.h functions</title>
<updated>2023-03-08T19:04:45+00:00</updated>
<author>
<name>David Tadokoro</name>
<email>davidbtadokoro@usp.br</email>
</author>
<published>2023-03-06T02:24:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=8bf0d9cdf36b0bebf17b733e3f5158783d765df3'/>
<id>8bf0d9cdf36b0bebf17b733e3f5158783d765df3</id>
<content type='text'>
The amdgpu_dm_plane.h functions didn't have names that indicated where
they were declared.

To better filter results in debug tools like ftrace, prefix these
functions with 'amdgpu_dm_plane_'.

Note that we may want to make this same change in other files like
amdgpu_dm_crtc.h.

Signed-off-by: David Tadokoro &lt;davidbtadokoro@usp.br&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The amdgpu_dm_plane.h functions didn't have names that indicated where
they were declared.

To better filter results in debug tools like ftrace, prefix these
functions with 'amdgpu_dm_plane_'.

Note that we may want to make this same change in other files like
amdgpu_dm_crtc.h.

Signed-off-by: David Tadokoro &lt;davidbtadokoro@usp.br&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/gpu: Add Multiplane Overlay doc</title>
<updated>2022-09-01T19:09:46+00:00</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-08-11T15:48:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=6c49df92faa2931ed7269e23a4c2740d3b8687e4'/>
<id>6c49df92faa2931ed7269e23a4c2740d3b8687e4</id>
<content type='text'>
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].

[1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/
[2]. https://lore.kernel.org/amd-gfx/864e45d0-c14b-3b12-0f5b-9d26a9cb41bd@amd.com/

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Cc: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Cc: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Cc: Simon Ser &lt;contact@emersion.fr&gt;
Cc: Pekka Paalanen &lt;pekka.paalanen@collabora.com&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Mark Yacoub &lt;markyacoub@chromium.org&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Pierre-Loup &lt;pgriffais@valvesoftware.com&gt;
Cc: Michel Dänzer &lt;michel.daenzer@mailbox.org&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].

[1]. https://lore.kernel.org/amd-gfx/3qY-QeukF_Q_MJeIXAuBjO4szbS4jRtqkTifXnbnN3bp88SxVodFQRpah3mIIVJq24DUkF6g0rOGdCmSqTvVxx9LCGEItmzLw8uWU44jtXE=@emersion.fr/
[2]. https://lore.kernel.org/amd-gfx/864e45d0-c14b-3b12-0f5b-9d26a9cb41bd@amd.com/

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Cc: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Cc: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Cc: Simon Ser &lt;contact@emersion.fr&gt;
Cc: Pekka Paalanen &lt;pekka.paalanen@collabora.com&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Mark Yacoub &lt;markyacoub@chromium.org&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Pierre-Loup &lt;pgriffais@valvesoftware.com&gt;
Cc: Michel Dänzer &lt;michel.daenzer@mailbox.org&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/gpu: Add an explanation about the DCN pipeline</title>
<updated>2022-09-01T19:09:39+00:00</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-08-11T15:48:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=330d6da3d03cca592d2101d0f25f01a611c4405b'/>
<id>330d6da3d03cca592d2101d0f25f01a611c4405b</id>
<content type='text'>
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.

Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Cc: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Cc: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Simon Ser &lt;contact@emersion.fr&gt;
Cc: Pekka Paalanen &lt;pekka.paalanen@collabora.com&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Mark Yacoub &lt;markyacoub@chromium.org&gt;
Cc: Pierre-Loup &lt;pgriffais@valvesoftware.com&gt;
Cc: Michel Dänzer &lt;michel.daenzer@mailbox.org&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.

Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.

Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
Cc: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Cc: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Cc: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Cc: Pierre-Eric Pelloux-Prayer &lt;pierre-eric.pelloux-prayer@amd.com&gt;
Cc: Leo Li &lt;sunpeng.li@amd.com&gt;
Cc: Simon Ser &lt;contact@emersion.fr&gt;
Cc: Pekka Paalanen &lt;pekka.paalanen@collabora.com&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Cc: Mark Yacoub &lt;markyacoub@chromium.org&gt;
Cc: Pierre-Loup &lt;pgriffais@valvesoftware.com&gt;
Cc: Michel Dänzer &lt;michel.daenzer@mailbox.org&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode</title>
<updated>2022-08-16T22:14:32+00:00</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2022-08-04T15:01:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=33fa4f1df53076d0078be091d5a88d457de54936'/>
<id>33fa4f1df53076d0078be091d5a88d457de54936</id>
<content type='text'>
AMD GPU display manager (DM) maps DRM pixel blend modes (None,
Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
options. Describe relevant elements and how to set and test them to get
the expected DRM blend mode on DCN hw.

v2:
- add ref tag (Tales)

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AMD GPU display manager (DM) maps DRM pixel blend modes (None,
Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
options. Describe relevant elements and how to set and test them to get
the expected DRM blend mode on DCN hw.

v2:
- add ref tag (Tales)

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drm/amd/display: add doc entries for MPC blending configuration</title>
<updated>2022-08-16T22:14:32+00:00</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2022-08-04T15:01:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=43d61f6d8f4d2da7df116eac4f83106ab1a29090'/>
<id>43d61f6d8f4d2da7df116eac4f83106ab1a29090</id>
<content type='text'>
Describe structs and enums used to set blend mode properties to MPC
blocks. Some pieces of information are already available as code
comments, and were just formatted. Others were collected and summarised
from discussions on AMD issue tracker[1][2].

[1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769

v2:
- fix typos (Tales)
- add MPCC to MPC entry in the glossary

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Describe structs and enums used to set blend mode properties to MPC
blocks. Some pieces of information are already available as code
comments, and were just formatted. Others were collected and summarised
from discussions on AMD issue tracker[1][2].

[1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769

v2:
- fix typos (Tales)
- add MPCC to MPC entry in the glossary

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/amdgpu/display: add DC color caps info</title>
<updated>2022-08-16T22:14:32+00:00</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2022-08-04T15:01:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=78e16ac1e764def96f4c89b433d379acd68881c7'/>
<id>78e16ac1e764def96f4c89b433d379acd68881c7</id>
<content type='text'>
Add details about color correction capabilities and explain a bit about
differences between DC hw generations and also how they are mapped
between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
to svg from the original png) is included to illustrate it. They were
obtained from a discussion[1] in the amd-gfx mailing list.

[1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/

v1:
- remove redundant comments (Harry)
- fix typos (Harry)

v2:
- reword introduction of color section
- add co-dev tag for Harry - who provided most of the info
- fix typos (Tales)
- describe missing struct parameters (Tales and Siqueira)

Co-developed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add details about color correction capabilities and explain a bit about
differences between DC hw generations and also how they are mapped
between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
to svg from the original png) is included to illustrate it. They were
obtained from a discussion[1] in the amd-gfx mailing list.

[1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/

v1:
- remove redundant comments (Harry)
- fix typos (Harry)

v2:
- reword introduction of color section
- add co-dev tag for Harry - who provided most of the info
- fix typos (Tales)
- describe missing struct parameters (Tales and Siqueira)

Co-developed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/amdgpu_dm: Add DM color correction documentation</title>
<updated>2022-08-16T22:14:32+00:00</updated>
<author>
<name>Melissa Wen</name>
<email>mwen@igalia.com</email>
</author>
<published>2022-08-04T15:01:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=cdeec9a11c3c95f33a3e2be36ef3fabd60b8ebf2'/>
<id>cdeec9a11c3c95f33a3e2be36ef3fabd60b8ebf2</id>
<content type='text'>
AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
to DC color correction entities. Part of this mapping is already
documented as code comments and can be converted as kernel docs.

v2:
- rebase to amd-staging-drm-next
- fix typos (Tales)
- undo kernel-docs inside functions (Tales)

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
to DC color correction entities. Part of this mapping is already
documented as code comments and can be converted as kernel docs.

v2:
- rebase to amd-staging-drm-next
- fix typos (Tales)
- undo kernel-docs inside functions (Tales)

Signed-off-by: Melissa Wen &lt;mwen@igalia.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Tales Aparecida &lt;tales.aparecida@gmail.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/gpu: include description of AMDGPU hardware structure</title>
<updated>2021-12-14T21:10:41+00:00</updated>
<author>
<name>Yann Dirson</name>
<email>ydirson@free.fr</email>
</author>
<published>2021-12-13T23:30:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=d59f1774bef998deaf3ff3fe1d2d3b069fea5aa2'/>
<id>d59f1774bef998deaf3ff3fe1d2d3b069fea5aa2</id>
<content type='text'>
This describes in broad lines the how an AMD GPU is organized, in
terms of hardware blocks.

This is Alex' description from the "gpu block diagram" thread, edited to
fit as ReST.

Original text: https://www.spinics.net/lists/amd-gfx/msg71543.html

Originally-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Yann Dirson &lt;ydirson@free.fr&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This describes in broad lines the how an AMD GPU is organized, in
terms of hardware blocks.

This is Alex' description from the "gpu block diagram" thread, edited to
fit as ReST.

Original text: https://www.spinics.net/lists/amd-gfx/msg71543.html

Originally-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Yann Dirson &lt;ydirson@free.fr&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Documentation/gpu: Add amdgpu and dc glossary</title>
<updated>2021-12-13T21:33:16+00:00</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2021-11-25T15:38:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=a723c6d0785acf9e4bf5b77167d6a0c32ecf8503'/>
<id>a723c6d0785acf9e4bf5b77167d6a0c32ecf8503</id>
<content type='text'>
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.

Changes since V3:
 - Yann: Add new acronyms to amdgpu glossary
 - Daniel: Add link between dc and amdgpu glossary

Changes since V2:
 - Add MMHUB

Changes since V1:
 - Yann: Divide glossary based on driver context.
 - Alex: Make terms more consistent and update CPLIB
 - Add new acronyms to the glossary

Reviewed-by: Yann Dirson &lt;ydirson@free.fr&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
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<pre>
In the DC driver, we have multiple acronyms that are not obvious most of
the time; the same idea is valid for amdgpu. This commit introduces a DC
and amdgpu glossary in order to make it easier to navigate through our
driver.

Changes since V3:
 - Yann: Add new acronyms to amdgpu glossary
 - Daniel: Add link between dc and amdgpu glossary

Changes since V2:
 - Add MMHUB

Changes since V1:
 - Yann: Divide glossary based on driver context.
 - Alex: Make terms more consistent and update CPLIB
 - Add new acronyms to the glossary

Reviewed-by: Yann Dirson &lt;ydirson@free.fr&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</pre>
</div>
</content>
</entry>
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