<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/arm/kernel/setup.c, branch v2.6.22-rc4</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>[ARM] 4387/1: fix /proc/cpuinfo formatting for pre-ARM7 parts</title>
<updated>2007-05-20T18:36:04+00:00</updated>
<author>
<name>Greg Ungerer</name>
<email>gerg@snapgear.com</email>
</author>
<published>2007-05-17T05:12:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=1d28bff7c4ea138032b44d514351b7caceb9fba5'/>
<id>1d28bff7c4ea138032b44d514351b7caceb9fba5</id>
<content type='text'>
Fix the formating of the "CPU part" field to be consistent with
the other fields for pre-ARM7 parts. One tab to many for them to
all line up.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix the formating of the "CPU part" field to be consistent with
the other fields for pre-ARM7 parts. One tab to many for them to
all line up.

Signed-off-by: Greg Ungerer &lt;gerg@uclinux.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] Fix breakage caused by 72486f1f8f0a2bc828b9d30cf4690cf2dd6807fc</title>
<updated>2007-03-13T09:54:21+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2007-03-13T09:54:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=66fb8bd209926140844830762164a44afdbf44ef'/>
<id>66fb8bd209926140844830762164a44afdbf44ef</id>
<content type='text'>
72486f1f8f0a2bc828b9d30cf4690cf2dd6807fc inverted the sense for
enabling hotplug CPU controls without reference to any other
architecture other than i386, ia64 and PowerPC.  This left
everyone else without hotplug CPU control.

Fix ARM for this brain damage.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
72486f1f8f0a2bc828b9d30cf4690cf2dd6807fc inverted the sense for
enabling hotplug CPU controls without reference to any other
architecture other than i386, ia64 and PowerPC.  This left
everyone else without hotplug CPU control.

Fix ARM for this brain damage.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm</title>
<updated>2007-02-19T21:18:39+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@woody.linux-foundation.org</email>
</author>
<published>2007-02-19T21:18:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=59b8175c771040afcd4ad67022b0cc80c216b866'/>
<id>59b8175c771040afcd4ad67022b0cc80c216b866</id>
<content type='text'>
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
  [ARM] 4058/2: iop32x: set -&gt;broken_parity_status on n2100 onboard r8169 ports
  [ARM] 4140/1: AACI stability add ac97 timeout and retries
  [ARM] 4139/1: AACI record support
  [ARM] 4138/1: AACI: multiple channel support for IRQ handling
  [ARM] 4211/1: Provide a defconfig for ns9xxx
  [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
  [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
  [ARM] 4221/1: S3C2443: DMA support
  [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
  [ARM] 4219/1: S3C2443: DMA source definitions
  [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
  [ARM] 4217/1: S3C24XX: remove the dma channel show at startup
  [ARM] 4090/2: avoid clash between PXA and SA1111 defines
  [ARM] 4216/1: add .gitignore entries for ARM specific files
  [ARM] 4214/2: S3C2410: Add Armzone QT2410
  [ARM] 4215/1: s3c2410 usb device:  per-platform vbus_draw
  [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
  [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
  [ARM] 4137/1: Add kexec support
  [ARM] 4201/1: SMP barriers pair needed for the secondary boot process
  ...

Fix up conflict due to typedef removal in sound/arm/aaci.h
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
  [ARM] 4058/2: iop32x: set -&gt;broken_parity_status on n2100 onboard r8169 ports
  [ARM] 4140/1: AACI stability add ac97 timeout and retries
  [ARM] 4139/1: AACI record support
  [ARM] 4138/1: AACI: multiple channel support for IRQ handling
  [ARM] 4211/1: Provide a defconfig for ns9xxx
  [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
  [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
  [ARM] 4221/1: S3C2443: DMA support
  [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
  [ARM] 4219/1: S3C2443: DMA source definitions
  [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
  [ARM] 4217/1: S3C24XX: remove the dma channel show at startup
  [ARM] 4090/2: avoid clash between PXA and SA1111 defines
  [ARM] 4216/1: add .gitignore entries for ARM specific files
  [ARM] 4214/2: S3C2410: Add Armzone QT2410
  [ARM] 4215/1: s3c2410 usb device:  per-platform vbus_draw
  [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
  [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
  [ARM] 4137/1: Add kexec support
  [ARM] 4201/1: SMP barriers pair needed for the secondary boot process
  ...

Fix up conflict due to typedef removal in sound/arm/aaci.h
</pre>
</div>
</content>
</entry>
<entry>
<title>[PATCH] Dynamic kernel command-line: arm</title>
<updated>2007-02-12T17:48:37+00:00</updated>
<author>
<name>Alon Bar-Lev</name>
<email>alon.barlev@gmail.com</email>
</author>
<published>2007-02-12T08:54:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=cd81899a7d9e77ffd5280b10d0413fb241b18388'/>
<id>cd81899a7d9e77ffd5280b10d0413fb241b18388</id>
<content type='text'>
1. Rename saved_command_line into boot_command_line.
2. Set command_line as __initdata.

Signed-off-by: Alon Bar-Lev &lt;alon.barlev@gmail.com&gt;
Cc: Russell King &lt;rmk@arm.linux.org.uk&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
1. Rename saved_command_line into boot_command_line.
2. Set command_line as __initdata.

Signed-off-by: Alon Bar-Lev &lt;alon.barlev@gmail.com&gt;
Cc: Russell King &lt;rmk@arm.linux.org.uk&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] 4134/1: Add generic support for outer caches</title>
<updated>2007-02-08T14:49:40+00:00</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2007-02-05T13:48:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=953233dc9958ba2b29753d0f24e37a33a076a5f6'/>
<id>953233dc9958ba2b29753d0f24e37a33a076a5f6</id>
<content type='text'>
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] 4054/1: ep93xx: add HWCAP_CRUNCH</title>
<updated>2006-12-18T00:14:54+00:00</updated>
<author>
<name>Lennert Buytenhek</name>
<email>buytenh@wantstofly.org</email>
</author>
<published>2006-12-17T23:59:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=99e4a6dda9dc4b863773c0a5857b762474b817cf'/>
<id>99e4a6dda9dc4b863773c0a5857b762474b817cf</id>
<content type='text'>
Add HWCAP_CRUNCH so that the dynamic linker knows whether it can
use Crunch-optimised libraries or not.

Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add HWCAP_CRUNCH so that the dynamic linker knows whether it can
use Crunch-optimised libraries or not.

Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] Handle HWCAP_VFP in VFP support code</title>
<updated>2006-12-08T16:05:26+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-12-08T15:22:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=efe90d273b6f365d37c0f82fbbd68a40982c3265'/>
<id>efe90d273b6f365d37c0f82fbbd68a40982c3265</id>
<content type='text'>
Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] Merge individual ARM sub-trees</title>
<updated>2006-12-07T23:07:26+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-12-07T23:07:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=6705cda24fad1cb0ac82ac4f312df8ec735b39b0'/>
<id>6705cda24fad1cb0ac82ac4f312df8ec735b39b0</id>
<content type='text'>
Merge:
 Atmel AT91RM9200 and AT91SAM9260 changes
 General ARM developments
 Disconfiguous memory cleanups
 64-bit/32-bit division and sched_clock extension patches
 EP93xx support changes
 IOP support changes

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Merge:
 Atmel AT91RM9200 and AT91SAM9260 changes
 General ARM developments
 Disconfiguous memory cleanups
 64-bit/32-bit division and sched_clock extension patches
 EP93xx support changes
 IOP support changes

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] Allow gcc to optimise arm_add_memory a little more</title>
<updated>2006-12-07T16:26:16+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk@dyn-67.arm.linux.org.uk</email>
</author>
<published>2006-11-30T20:44:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=05f96ef1189ecbf2e8548056a0ca016e4f630cef'/>
<id>05f96ef1189ecbf2e8548056a0ca016e4f630cef</id>
<content type='text'>
For some reason, gcc was calculating meminfo.bank[meminfo.nr_banks]
repeatedly.  Use a pointer to it instead.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For some reason, gcc was calculating meminfo.bank[meminfo.nr_banks]
repeatedly.  Use a pointer to it instead.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[ARM] 3881/4: xscale: clean up cp0/cp1 handling</title>
<updated>2006-12-03T17:52:22+00:00</updated>
<author>
<name>Lennert Buytenhek</name>
<email>buytenh@wantstofly.org</email>
</author>
<published>2006-12-03T17:51:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=afe4b25e7d9260d85fccb2d13c9933a987bdfc8a'/>
<id>afe4b25e7d9260d85fccb2d13c9933a987bdfc8a</id>
<content type='text'>
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Acked-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek &lt;buytenh@wantstofly.org&gt;
Acked-by: Dan Williams &lt;dan.j.williams@intel.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
</feed>
