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<title>linux.git/arch/arm/kernel/traps.c, branch v3.14.29</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>ARM: 8226/1: cacheflush: get rid of restarting block</title>
<updated>2014-12-06T23:55:37+00:00</updated>
<author>
<name>Vladimir Murzin</name>
<email>vladimir.murzin@arm.com</email>
</author>
<published>2014-11-27T10:39:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=9f285205f1e4e5a1c840bcf0f27bc9b91e95912a'/>
<id>9f285205f1e4e5a1c840bcf0f27bc9b91e95912a</id>
<content type='text'>
commit 3f4aa45ceea5789a4aade536acc27f2e0d3da5e1 upstream.

We cannot restart cacheflush safely if a process provides user-defined
signal handler and signal is pending. In this case -EINTR is returned
and it is expected that process re-invokes syscall. However, there are
a few problems with that:
 * looks like nobody bothers checking return value from cacheflush
 * but if it did, we don't provide the restart address for that, so the
   process has to use the same range again
 * ...and again, what might lead to looping forever

So, remove cacheflush restarting code and terminate cache flushing
as early as fatal signal is pending.

Reported-by: Chanho Min &lt;chanho.min@lge.com&gt;
Signed-off-by: Vladimir Murzin &lt;vladimir.murzin@arm.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

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commit 3f4aa45ceea5789a4aade536acc27f2e0d3da5e1 upstream.

We cannot restart cacheflush safely if a process provides user-defined
signal handler and signal is pending. In this case -EINTR is returned
and it is expected that process re-invokes syscall. However, there are
a few problems with that:
 * looks like nobody bothers checking return value from cacheflush
 * but if it did, we don't provide the restart address for that, so the
   process has to use the same range again
 * ...and again, what might lead to looping forever

So, remove cacheflush restarting code and terminate cache flushing
as early as fatal signal is pending.

Reported-by: Chanho Min &lt;chanho.min@lge.com&gt;
Signed-off-by: Vladimir Murzin &lt;vladimir.murzin@arm.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 8148/1: flush TLS and thumbee register state during exec</title>
<updated>2014-10-05T21:52:16+00:00</updated>
<author>
<name>Nathan Lynch</name>
<email>nathan_lynch@mentor.com</email>
</author>
<published>2014-09-11T01:49:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=d164cc67d028228ac8f216930aec3442c47321bc'/>
<id>d164cc67d028228ac8f216930aec3442c47321bc</id>
<content type='text'>
commit fbfb872f5f417cea48760c535e0ff027c88b507a upstream.

The TPIDRURO and TPIDRURW registers need to be flushed during exec;
otherwise TLS information is potentially leaked.  TPIDRURO in
particular needs careful treatment.  Since flush_thread basically
needs the same code used to set the TLS in arm_syscall, pull that into
a common set_tls helper in tls.h and use it in both places.

Similarly, TEEHBR needs to be cleared during exec as well.  Clearing
its save slot in thread_info isn't right as there is no guarantee
that a thread switch will occur before the new program runs.  Just
setting the register directly is sufficient.

Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

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<pre>
commit fbfb872f5f417cea48760c535e0ff027c88b507a upstream.

The TPIDRURO and TPIDRURW registers need to be flushed during exec;
otherwise TLS information is potentially leaked.  TPIDRURO in
particular needs careful treatment.  Since flush_thread basically
needs the same code used to set the TLS in arm_syscall, pull that into
a common set_tls helper in tls.h and use it in both places.

Similarly, TEEHBR needs to be cleared during exec as well.  Clearing
its save slot in thread_info isn't right as there is no guarantee
that a thread switch will occur before the new program runs.  Just
setting the register directly is sufficient.

Signed-off-by: Nathan Lynch &lt;nathan_lynch@mentor.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'amba', 'fixes', 'kees', 'misc' and 'unstable/sa11x0' into for-next</title>
<updated>2014-01-21T21:26:33+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-01-21T21:26:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=6f14d778c15fe08b6d98e759cf7e3893ed67b238'/>
<id>6f14d778c15fe08b6d98e759cf7e3893ed67b238</id>
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<pre>
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</entry>
<entry>
<title>ARM: 7939/1: traps: fix opcode endianness when read from user memory</title>
<updated>2014-01-11T12:06:59+00:00</updated>
<author>
<name>Taras Kondratiuk</name>
<email>taras.kondratiuk@linaro.org</email>
</author>
<published>2014-01-10T00:36:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=d6cd989477e2fee29ccda257614ef7b2621d0601'/>
<id>d6cd989477e2fee29ccda257614ef7b2621d0601</id>
<content type='text'>
Currently code has an inverted logic: opcode from user memory
is swapped to a proper endianness only in case of read error.
While normally opcode should be swapped only if it was read
correctly from user memory.

Reviewed-by: Victor Kamensky &lt;victor.kamensky@linaro.org&gt;
Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Signed-off-by: Taras Kondratiuk &lt;taras.kondratiuk@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Currently code has an inverted logic: opcode from user memory
is swapped to a proper endianness only in case of read error.
While normally opcode should be swapped only if it was read
correctly from user memory.

Reviewed-by: Victor Kamensky &lt;victor.kamensky@linaro.org&gt;
Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Signed-off-by: Taras Kondratiuk &lt;taras.kondratiuk@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: fix "bad mode in ... handler" message for undefined instructions</title>
<updated>2014-01-05T14:00:00+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-01-03T15:01:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=29c350bf28da333e41e30497b649fe335712a2ab'/>
<id>29c350bf28da333e41e30497b649fe335712a2ab</id>
<content type='text'>
The array was missing the final entry for the undefined instruction
exception handler; this commit adds it.

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
The array was missing the final entry for the undefined instruction
exception handler; this commit adds it.

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: make kernel oops easier to read</title>
<updated>2013-12-29T12:32:30+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2013-10-20T14:34:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=ef41b5c924984b34d9c2830185295b2a9ae78e13'/>
<id>ef41b5c924984b34d9c2830185295b2a9ae78e13</id>
<content type='text'>
We don't need the offset for the first function name in each backtrace
entry; this needlessly consumes screen space.  This is virtually always
the first or second instruction in the called function.

Also, recognise stmfd instructions which include r10 as a valid stack
saving instruction, and when dumping the registers, dump six registers
per line rather than five, and fix the wrapping.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
We don't need the offset for the first function name in each backtrace
entry; this needlessly consumes screen space.  This is virtually always
the first or second instruction in the called function.

Also, recognise stmfd instructions which include r10 as a valid stack
saving instruction, and when dumping the registers, dump six registers
per line rather than five, and fix the wrapping.

Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7917/1: cacheflush: correctly limit range of memory region being flushed</title>
<updated>2013-12-09T23:24:35+00:00</updated>
<author>
<name>Jon Medhurst</name>
<email>tixy@linaro.org</email>
</author>
<published>2013-12-09T12:45:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=b31459adeab018b297541e288ac88873011da82a'/>
<id>b31459adeab018b297541e288ac88873011da82a</id>
<content type='text'>
The __do_cache_op function operates with a 'chunk' size of one page
but fails to limit the size of the final chunk so as to not exceed
the specified memory region. Fix this.

Cc: &lt;stable@vger.kernel.org&gt;
Reported-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Tested-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
The __do_cache_op function operates with a 'chunk' size of one page
but fails to limit the size of the final chunk so as to not exceed
the specified memory region. Fix this.

Cc: &lt;stable@vger.kernel.org&gt;
Reported-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Tested-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Jon Medhurst &lt;tixy@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7892/1: Fix warning for V7M builds</title>
<updated>2013-11-19T00:41:03+00:00</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2013-11-18T05:01:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=5761704a41c63ebe756295a13d2e236280dd8a86'/>
<id>5761704a41c63ebe756295a13d2e236280dd8a86</id>
<content type='text'>
Fixes a harmless warning when building for V7M (!MMU):
 arch/arm/kernel/traps.c:859:123: warning: 'kuser_init' defined but not used [-Wunused-function]

By making the stub static inline instead of just static.

Fixes: f6f91b0d9fd9 ('ARM: allow kuser helpers to be removed from the vector page')

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
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<pre>
Fixes a harmless warning when building for V7M (!MMU):
 arch/arm/kernel/traps.c:859:123: warning: 'kuser_init' defined but not used [-Wunused-function]

By making the stub static inline instead of just static.

Fixes: f6f91b0d9fd9 ('ARM: allow kuser helpers to be removed from the vector page')

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Correct BUG() assembly to ensure it is endian-agnostic</title>
<updated>2013-10-19T19:46:35+00:00</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@codethink.co.uk</email>
</author>
<published>2013-07-25T13:38:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=63328070eff2f4fd730c86966a0dbc976147c39f'/>
<id>63328070eff2f4fd730c86966a0dbc976147c39f</id>
<content type='text'>
Currently BUG() uses .word or .hword to create the necessary illegal
instructions. However if we are building BE8 then these get swapped
by the linker into different illegal instructions in the text. This
means that the BUG() macro does not get trapped properly.

Change to using &lt;asm/opcodes.h&gt; to provide the necessary ARM instruction
building as we cannot rely on gcc/gas having the `.inst` instructions
which where added to try and resolve this issue (reported by Dave Martin
&lt;Dave.Martin@arm.com&gt;).

Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Reviewed-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</content>
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<pre>
Currently BUG() uses .word or .hword to create the necessary illegal
instructions. However if we are building BE8 then these get swapped
by the linker into different illegal instructions in the text. This
means that the BUG() macro does not get trapped properly.

Change to using &lt;asm/opcodes.h&gt; to provide the necessary ARM instruction
building as we cannot rely on gcc/gas having the `.inst` instructions
which where added to try and resolve this issue (reported by Dave Martin
&lt;Dave.Martin@arm.com&gt;).

Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Reviewed-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: traps: use &lt;asm/opcodes.h&gt; to get correct instruction order</title>
<updated>2013-10-19T19:46:34+00:00</updated>
<author>
<name>Ben Dooks</name>
<email>ben.dooks@codethink.co.uk</email>
</author>
<published>2013-07-19T16:12:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=a79a0cb1d35ec422dcf493cef1bebf9fdfcfdb9a'/>
<id>a79a0cb1d35ec422dcf493cef1bebf9fdfcfdb9a</id>
<content type='text'>
The trap handler needs to take into account the endian configuration of
the system when loading instructions. Use &lt;asm/opcodes.h&gt; to provide the
necessary conversion functions.

Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Tested-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
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<pre>
The trap handler needs to take into account the endian configuration of
the system when loading instructions. Use &lt;asm/opcodes.h&gt; to provide the
necessary conversion functions.

Signed-off-by: Ben Dooks &lt;ben.dooks@codethink.co.uk&gt;
Tested-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</pre>
</div>
</content>
</entry>
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