linux.git/arch/arm64, branch v6.15.10

bpf, arm64: Fix fp initialization for exception boundary

2025-08-15T10:16:37+00:00

[ Upstream commit b114fcee766d5101eada1aca7bb5fd0a86c89b35 ]

In the ARM64 BPF JIT when prog->aux->exception_boundary is set for a BPF
program, find_used_callee_regs() is not called because for a program
acting as exception boundary, all callee saved registers are saved.
find_used_callee_regs() sets `ctx->fp_used = true;` when it sees FP
being used in any of the instructions.

For programs acting as exception boundary, ctx->fp_used remains false
even if frame pointer is used by the program and therefore, FP is not
set-up for such programs in the prologue. This can cause the kernel to
crash due to a pagefault.

Fix it by setting ctx->fp_used = true for exception boundary programs as
fp is always saved in such programs.

Fixes: 5d4fa9ec5643 ("bpf, arm64: Avoid blindly saving/restoring all callee-saved registers")
Signed-off-by: Puranjay Mohan 
Signed-off-by: Daniel Borkmann 
Acked-by: Xu Kuohai 
Link: https://lore.kernel.org/bpf/20250722133410.54161-2-puranjay@kernel.org
Signed-off-by: Sasha Levin

arm64/gcs: task_gcs_el0_enable() should use passed task

2025-08-15T10:16:34+00:00

[ Upstream commit cbbcfb94c55c02a8c4ce52b5da0770b5591a314c ]

Mark Rutland noticed that the task parameter is ignored and
'current' is being used instead. Since this is usually
what its passed, it hasn't yet been causing problems but likely
will as the code gets more testing.

But, once this is fixed, it creates a new bug in copy_thread_gcs()
since the gcs_el_mode isn't yet set for the task before its being
checked. Move gcs_alloc_thread_stack() after the new task's
gcs_el0_mode initialization to avoid this.

Fixes: fc84bc5378a8 ("arm64/gcs: Context switch GCS state for EL0")
Signed-off-by: Jeremy Linton 
Reviewed-by: Mark Brown 
Link: https://lore.kernel.org/r/20250719043740.4548-2-jeremy.linton@arm.com
Signed-off-by: Catalin Marinas 
Signed-off-by: Sasha Levin

arm64: dts: rockchip: Fix pinctrl node names for RK3528

2025-08-15T10:16:21+00:00

[ Upstream commit f2792bf1c7a54ef23fb3a84286b66f427bfc4853 ]

Following warnings can be observed with CHECK_DTBS=y for the RK3528:

  rk3528-pinctrl.dtsi:101.36-105.5: Warning (node_name_chars_strict):
    /pinctrl/fephy/fephym0-led_dpx: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:108.38-112.5: Warning (node_name_chars_strict):
    /pinctrl/fephy/fephym0-led_link: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:115.36-119.5: Warning (node_name_chars_strict):
    /pinctrl/fephy/fephym0-led_spd: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:122.36-126.5: Warning (node_name_chars_strict):
   /pinctrl/fephy/fephym1-led_dpx: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:129.38-133.5: Warning (node_name_chars_strict):
    /pinctrl/fephy/fephym1-led_link: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:136.36-140.5: Warning (node_name_chars_strict):
    /pinctrl/fephy/fephym1-led_spd: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:782.32-790.5: Warning (node_name_chars_strict):
    /pinctrl/rgmii/rgmii-rx_bus2: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:793.32-801.5: Warning (node_name_chars_strict):
    /pinctrl/rgmii/rgmii-tx_bus2: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:804.36-810.5: Warning (node_name_chars_strict):
    /pinctrl/rgmii/rgmii-rgmii_clk: Character '_' not recommended in node name
  rk3528-pinctrl.dtsi:813.36-823.5: Warning (node_name_chars_strict):
    /pinctrl/rgmii/rgmii-rgmii_bus: Character '_' not recommended in node name

Rename the affected nodes to fix these warnings.

Fixes: a31fad19ae39 ("arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528")
Signed-off-by: Jonas Karlman 
Link: https://lore.kernel.org/r/20250621113859.2146400-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed

2025-08-15T10:16:21+00:00

[ Upstream commit e16ad6c79906bba5e2ac499492b6a5b29ab19d6c ]

The reference manual for the i.MX8MN states the clock rate in
MMC mode is 1/2 of the input clock, therefore to properly run
at HS400 rates, the input clock must be 400MHz to operate at
200MHz.  Currently the clock is set to 200MHz which is half the
rate it should be, so the throughput is half of what it should be
for HS400 operation.

Fixes: 36ca3c8ccb53 ("arm64: dts: imx: Add Beacon i.MX8M Nano development kit")
Signed-off-by: Adam Ford 
Reviewed-by: Fabio Estevam 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed

2025-08-15T10:16:21+00:00

[ Upstream commit f83f69097a302ed2a2775975ddcf12e6a5ac6ec3 ]

The reference manual for the i.MX8MM states the clock rate in
MMC mode is 1/2 of the input clock, therefore to properly run
at HS400 rates, the input clock must be 400MHz to operate at
200MHz.  Currently the clock is set to 200MHz which is half the
rate it should be, so the throughput is half of what it should be
for HS400 operation.

Fixes: 593816fa2f35 ("arm64: dts: imx: Add Beacon i.MX8m-Mini development kit")
Signed-off-by: Adam Ford 
Reviewed-by: Fabio Estevam 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

arm64: dts: st: fix timer used for ticks

2025-08-15T10:16:20+00:00

[ Upstream commit 9ec406ac4b7de3e8040a503429d1a5d389bfdaf6 ]

Remove always-on on generic ARM timer as the clock source provided by
STGEN is deactivated in low power mode, STOP1 by example.

Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family")
Signed-off-by: Patrick Delaunay 
Link: https://lore.kernel.org/r/20250515151238.1.I85271ddb811a7cf73532fec90de7281cb24ce260@changeid
Signed-off-by: Alexandre Torgue 
Signed-off-by: Sasha Levin

arm64: dts: rockchip: fix PHY handling for ROCK 4D

2025-08-15T10:16:20+00:00

[ Upstream commit cd803da7c033e376a66793a43ee98e136bc6cc25 ]

Old revisions of the ROCK 4D board have a dedicated crystal to
supply the RTL8211F PHY's 25MHz clock input. At least some newer
revisions instead use REFCLKO25M_GMAC0_OUT. The DT already has
this half-prepared, but there are some issues:

1. The DT relies on auto-selecting the right PHY driver, which
   requires that it works good enough to read the ID registers.
   This does not work without the clock, which is handled by
   the PHY driver. By updating the compatible to contain the
   RTL8211F IDs, so that the operating system can choose the
   right PHY driver without relying on a pre-powered PHY.

2. Despite the name REFCLKO25M_GMAC0_OUT could also provide a
   different frequency, so ensure it is explicitly set to 25
   MHz as expected by the PHY.

3. While at it switch from deprecated "enable-gpio" to standard
   "enable-gpios".

Fixes: a0fb7eca9c09 ("arm64: dts: rockchip: Add Radxa ROCK 4D device tree")
Signed-off-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20250704-rk3576-rock4d-phy-handling-fixes-v1-1-1d64130c4139@kernel.org
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpio

2025-08-15T10:16:19+00:00

[ Upstream commit 26a6a9cde64a890997708007d9de25809970eac9 ]

The GW74xx D revision has added a M2SKT_WDIS2# GPIO which routes to the
W_DISABLE2# pin of the M.2 socket. Update the gpio name for consistency.

Fixes: 6a5d95b06d93 ("arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration")
Signed-off-by: Tim Harvey 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C

2025-08-15T10:16:18+00:00

[ Upstream commit 6e3071f4e03997ca0e4388ca61aa06df2802dcd1 ]

eMMC HS200 mode (1.8V I/O) is supported by the MMC host controller on
RK3528 and works with the optional on-board eMMC module on Radxa E20C.

Be explicit about HS200 support in the device tree for Radxa E20C.

Fixes: 3a01b5f14a8a ("arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C")
Signed-off-by: Jonas Karlman 
Link: https://lore.kernel.org/r/20250621165832.2226160-1-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner 
Signed-off-by: Sasha Levin

arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single size

2025-08-15T10:16:17+00:00

[ Upstream commit fdc8ad019ab9a2308b8cef54fbc366f482fb746f ]

Pinmux registers ends at 0x000f42ac (including). Thus, the size argument
of the pinctrl-single node has to be 0x2b0. Fix it.

This will fix the following error:
pinctrl-single f4000.pinctrl: mux offset out of range: 0x2ac (0x2ac)

Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs")
Signed-off-by: Michael Walle 
Link: https://lore.kernel.org/r/20250618065239.1904953-1-mwalle@kernel.org
Signed-off-by: Vignesh Raghavendra 
Signed-off-by: Sasha Levin