linux.git/arch/mips/boot/dts, branch v4.19.259

MIPS: dts: ar9331: fix interrupt-controller size

2019-10-29T08:19:32+00:00

[ Upstream commit 0889d07f3e4b171c453b2aaf2b257f9074cdf624 ]

It is two registers each of 4 byte.

Signed-off-by: Oleksij Rempel 
Signed-off-by: Paul Burton 
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Pengutronix Kernel Team 
Cc: Ralf Baechle 
Cc: James Hogan 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Sasha Levin

DTS: CI20: Fix bugs in ci20's device tree.

2019-03-13T21:02:34+00:00

[ Upstream commit 1ca1c87f91d9dc50d6a38e2177b2032996e7901c ]

According to the Schematic, the hardware of ci20 leads to uart3,
but not to uart2. Uart2 is miswritten in the original code.

Signed-off-by: Zhou Yanjie 
Signed-off-by: Paul Burton 
Cc: linux-mips 
Cc: linux-kernel 
Cc: devicetree@vger.kernel.org
Cc: robh+dt@kernel.org
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: mark.rutland@arm.com
Cc: malat@debian.org
Cc: ezequiel@collabora.co.uk
Cc: ulf.hansson@linaro.org
Cc: syq 
Cc: jiaxun.yang 
Signed-off-by: Sasha Levin

MIPS: Boston: Disable EG20T prefetch

2019-02-12T18:46:59+00:00

[ Upstream commit 5ec17af7ead09701e23d2065e16db6ce4e137289 ]

The Intel EG20T Platform Controller Hub used on the MIPS Boston
development board supports prefetching memory to optimize DMA transfers.
Unfortunately for unknown reasons this doesn't work well with some MIPS
CPUs such as the P6600, particularly when using an I/O Coherence Unit
(IOCU) to provide cache-coherent DMA. In these systems it is common for
DMA data to be lost, resulting in broken access to EG20T devices such as
the MMC or SATA controllers.

Support for a DT property to configure the prefetching was added a while
back by commit 549ce8f134bd ("misc: pch_phub: Read prefetch value from
device tree if passed") but we never added the DT snippet to make use of
it. Add that now in order to disable the prefetching & fix DMA on the
affected systems.

Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/21068/
Cc: linux-mips@linux-mips.org
Signed-off-by: Sasha Levin

mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123

2018-07-31T17:34:34+00:00

Ocelot PCB123 has a SPI NOR connected on its SPI bus.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20103/
Cc: Mark Brown 
Cc: James Hogan 
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni 
Cc: Allan Nielsen

mips: dts: mscc: Add spi on Ocelot

2018-07-31T17:34:08+00:00

Add support for the SPI controller

Signed-off-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20101/
Cc: Mark Brown 
Cc: James Hogan 
Cc: linux-spi@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Thomas Petazzoni 
Cc: Allan Nielsen

MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller

2018-07-30T17:34:28+00:00

The GPIO controller also serves as an interrupt controller for events
on the GPIO it handles.

An interrupt occurs whenever a GPIO line has changed.

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Reviewed-by: Linus Walleij 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20015/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com

MIPS: ath79: Use the IRQ based GPIO key driver for the buttons

2018-07-28T02:29:53+00:00

Now that the GPIO driver support interrupts we don't need to poll the
buttons.

Signed-off-by: Alban Bedel 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/15283/
Cc: linux-mips@linux-mips.org
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Ralf Baechle 
Cc: Antony Pavlov 
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

MIPS: ath79: Fix the USB PHY reset names

2018-07-26T18:21:28+00:00

The binding for the USB PHY went thru before the driver. However the
new version of the driver now use the PHY core support for reset, and
this expect the reset to be named "phy". So remove the "usb-" prefix
from the the reset names.

Signed-off-by: Alban Bedel 
Acked-by: Rob Herring 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/15282/
Cc: linux-kernel@vger.kernel.org
Cc: Rob Herring 
Cc: Mark Rutland 
Cc: Ralf Baechle 
Cc: Antony Pavlov 
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org

MIPS: mscc: ocelot: add MIIM1 bus

2018-07-26T17:35:19+00:00

There is an additional MIIM (MDIO) bus in this SoC so let's declare it
in the dtsi.

This bus requires GPIO 14 and 15 pins that need to be muxed. There is no
support for internal PHY reset on this bus on the contrary of MIIM0 so
there is only one register address space and not two.

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20014/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com

MIPS: mscc: ocelot: fix length of memory address space for MIIM

2018-07-26T17:34:58+00:00

The length of memory address space for MIIM0 is from 0x7107009c to
0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in
hexadecimal and not 0x36.

Fixes: 49b031690abe ("MIPS: mscc: Add switch to ocelot")

Signed-off-by: Quentin Schulz 
Acked-by: Alexandre Belloni 
Signed-off-by: Paul Burton 
Patchwork: https://patchwork.linux-mips.org/patch/20013/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com