linux.git/arch/mips/kernel/branch.c, branch v3.16.81

MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn'

2017-10-12T14:27:57+00:00

commit 7b82c1058ac1f8f8b9f2b8786b1f710a57a870a8 upstream.

Fix commit e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.") and
send SIGILL rather than SIGBUS whenever an unimplemented BPOSGE32 DSP
ASE instruction has been encountered in `__compute_return_epc_for_insn'
as our Reserved Instruction exception handler would in response to an
attempt to actually execute the instruction.  Sending SIGBUS only makes
sense for the unaligned PC case, since moved to `__compute_return_epc'.
Adjust function documentation accordingly, correct formatting and use
`pr_info' rather than `printk' as the other exit path already does.

Fixes: e50c0a8fa60d ("Support the MIPS32 / MIPS64 DSP ASE.")
Signed-off-by: Maciej W. Rozycki 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16396/
Signed-off-by: Ralf Baechle 
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings

MIPS: Actually decode JALX in `__compute_return_epc_for_insn'

2017-10-12T14:27:56+00:00

commit a9db101b735a9d49295326ae41f610f6da62b08c upstream.

Complement commit fb6883e5809c ("MIPS: microMIPS: Support handling of
delay slots.") and actually decode the regular MIPS JALX major
instruction opcode, the handling of which has been added with the said
commit for EPC calculation in `__compute_return_epc_for_insn'.

Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.")
Signed-off-by: Maciej W. Rozycki 
Cc: James Hogan 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16394/
Signed-off-by: Ralf Baechle 
Signed-off-by: Ben Hutchings

MIPS: Fix build with binutils 2.24.51+

2017-04-04T21:21:53+00:00

commit 842dfc11ea9a21f9825167c8a4f2834b205b0a79 upstream.

Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.

Signed-off-by: Manuel Lauss 
Cc: Linux-MIPS 
Cc: Matthew Fortune 
Cc: Markos Chandras 
Cc: Maciej W. Rozycki 
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle 
Signed-off-by: Ben Hutchings 
Cc: Arnd Bergmann

Merge branch '3.15-fixes' into mips-for-linux-next

2014-06-04T20:53:02+00:00

MIPS: OCTEON: Enable use of FPU

2014-05-30T19:01:09+00:00

Some versions of the assembler will not assemble CFC1 for OCTEON, so
override the ISA for these.

Add r4k_fpu.o to handle low level FPU initialization.

Modify octeon_switch.S to save the FPU registers.  And include
r4k_switch.S to pick up more FPU support.

Get rid of "#define cpu_has_fpu		0"

Signed-off-by: David Daney 
Signed-off-by: Andreas Herrmann 
Cc: linux-mips@linux-mips.org
Cc: James Hogan 
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7006/
Signed-off-by: Ralf Baechle

MIPS: Sort out mm_isBranchInstr.

2014-05-23T13:12:37+00:00

mm_isBranchInstr() did reside in the math emu code even though it logically
is separate and also is used outside the math emu code.  In addition GCC 4.9.0
leaves the following unnnecessarily bloated function body for a non-microMIPS
configuration:

:
    105c:       afa50004        sw      a1,4(sp)
    1060:       afa60008        sw      a2,8(sp)
    1064:       afa7000c        sw      a3,12(sp)
    1068:       03e00008        jr      ra
    106c:       00001021        move    v0,zero

which stores arguments that are never going to be used on the stack frame.

Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr()
into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function
which only invokes __mm_isBranchInstr() on microMIPS configurations.

This shaves off 112 bytes off the kernel and improves code flow a bit.

Signed-off-by: Ralf Baechle

MIPS: Fix branch emulation of branch likely instructions.

2014-05-22T23:00:26+00:00

Two issues:

  o For beql_op, beql_op, bne_op, bnel_op, blez_op, blezl_op, bgtz_op and
    bgtzl_op the wrong field was being checked for the instruction opcode.
  o For blez_op / blezl_op and bgtz_op / bgtzl_op the test was testing
    for the wrong opcode.

This bug got introduced by d8d4e3ae0b5c179c0bfd3f0af5b352d13bea9cfa [MIPS
Kprobes: Refactor branch emulation].

Signed-off-by: Ralf Baechle 
Acked-by: Leonid Yegoshin 
Acked-by: Victor Kamensky

MIPS: Cleanup indentation and whitespace

2013-07-01T13:10:57+00:00

Signed-off-by: Tony Wu 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5536/
Signed-off-by: Ralf Baechle

MIPS: MIPS16e: Support handling of delay slots.

2013-05-09T15:55:20+00:00

Add logic needed to properly calculate exceptions for delay slots
when in MIPS16e mode.

Signed-off-by: Steven J. Hill

MIPS: microMIPS: Support handling of delay slots.

2013-05-09T15:55:18+00:00

Add logic needed to properly calculate exceptions for delay slots
when in microMIPS mode.

Signed-off-by: Leonid Yegoshin 
Signed-off-by: Steven J. Hill