linux.git/arch/mips/kernel/traps.c, branch v4.16.13

signal: Don't use structure initializers for struct siginfo

2018-01-23T01:07:08+00:00

The siginfo structure has all manners of holes with the result that a
structure initializer is not guaranteed to initialize all of the bits.
As we have to copy the structure to userspace don't even try to use
a structure initializer.  Instead use clear_siginfo followed by initializing
selected fields.  This gives a guarantee that uninitialized kernel memory
is not copied to userspace.

Signed-off-by: "Eric W. Biederman"

Pass mode to wait_on_atomic_t() action funcs and provide default actions

2017-11-13T15:38:16+00:00

Make wait_on_atomic_t() pass the TASK_* mode onto its action function as an
extra argument and make it 'unsigned int throughout.

Also, consolidate a bunch of identical action functions into a default
function that can do the appropriate thing for the mode.

Also, change the argument name in the bit_wait*() function declarations to
reflect the fact that it's the mode and not the bit number.

[Peter Z gives this a grudging ACK, but thinks that the whole atomic_t wait
should be done differently, though he's not immediately sure as to how]

Signed-off-by: David Howells 
Acked-by: Peter Zijlstra 
cc: Ingo Molnar

MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers

2017-08-29T22:57:27+00:00

With Coherence Manager (CM) 3.5 information about the topology of the
system, which has previously only been available through & accessed from
the CM, is now also provided by the Cluster Power Controller (CPC). This
includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a
new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG.

In preparation for adjusting functions such as mips_cm_numcores(), which
have previously only needed to access the CM, to also access the CPC
this patch modifies the way we use the various CPS headers. Rather than
having users include asm/mips-cm.h or asm/mips-cpc.h individually we
instead have users include asm/mips-cps.h which in turn includes
asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access
to both CM & CPC registers by including one header, and most importantly
it makes asm/mips-cps.h an ideal location for helper functions which
need to access the various components of the CPS.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17015/
Patchwork: https://patchwork.linux-mips.org/patch/17217/
Signed-off-by: Ralf Baechle

MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts

2017-08-29T13:21:57+00:00

There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h
when declaring macros corresponding to register fields. This patch
modifies our definitions to do so.

The *_SHF definitions are removed entirely - they duplicate information
found in the masks, are infrequently used & can be replaced with use of
__ffs() where needed.

The *_MSK definitions then lose their _MSK suffix which is now somewhat
redundant, and users are modified to match.

The field definitions are moved to follow the appropriate register's
accessor functions, which helps to keep the field definitions in order &
to find the appropriate fields for a given register. Whilst here a
comment is added describing each register & including its name, which is
helpful both for linking the register back to hardware documentation &
for grepping purposes.

This also cleans up a couple of issues that became obvious as a result
of making the changes described above:

  - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony
    copy of that named GCR_RESET_EXT_BASE - a register which does not
    exist. The bad definitions were added by commit 497e803ebf98 ("MIPS:
    smp-cps: Ensure secondary cores start with EVA disabled") and made
    use of from boot_core(), which is now modified to use the
    GCR_Cx_RESET_EXT_BASE definitions.

  - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly
    define this as inFo rather than inGo.

Now that we don't duplicate field information between _SHF & _MSK
definitions, and keep the fields next to the register accessors, it will
be much easier to spot & prevent any similar oddities being introduced
in the future.

Signed-off-by: Paul Burton 
Acked-by: Thomas Gleixner

MIPS: signal: Remove unreachable code from force_fcr31_sig().

2017-08-29T13:21:52+00:00

Based on discussion with Linus remove the impossible to reach code
rather than replacing it with a BUG().

Signed-off-by: Ralf Baechle 
Link: http://lkml.kernel.org/r/20170718140651.15973-4-ebiederm@xmission.com

MIPS: Remove unused R6000 support

2017-08-29T13:21:51+00:00

The kernel contains a small amount of incomplete code aimed at
supporting old R6000 CPUs. This is:

  - Unused, as no machine selects CONFIG_SYS_HAS_CPU_R6000.

  - Broken, since there are glaring errors such as r6000_fpu.S moving
    the FCSR register to t1, then ignoring it & instead saving t0 into
    struct sigcontext...

  - A maintenance headache, since it's code that nobody can test which
    nevertheless imposes constraints on code which it shares with other
    machines.

Remove this incomplete & broken R6000 CPU support in order to clean up
and in preparation for changes which will no longer need to consider
dragging the pretense of R6000 support along with them.

Signed-off-by: Paul Burton 
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16236/
Signed-off-by: Ralf Baechle

lib/extable.c: use bsearch() library function in search_extable()

2017-07-10T23:32:35+00:00

[thomas@m3y3r.de: v3: fix arch specific implementations]
  Link: http://lkml.kernel.org/r/1497890858.12931.7.camel@m3y3r.de
Signed-off-by: Thomas Meyer 
Cc: Rasmus Villemoes 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

MIPS: Avoid accidental raw backtrace

2017-06-30T02:42:15+00:00

Since commit 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with
usermode") show_backtrace() invokes the raw backtracer when
cp0_status & ST0_KSU indicates user mode to fix issues on EVA kernels
where user and kernel address spaces overlap.

However this is used by show_stack() which creates its own pt_regs on
the stack and leaves cp0_status uninitialised in most of the code paths.
This results in the non deterministic use of the raw back tracer
depending on the previous stack content.

show_stack() deals exclusively with kernel mode stacks anyway, so
explicitly initialise regs.cp0_status to KSU_KERNEL (i.e. 0) to ensure
we get a useful backtrace.

Fixes: 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with usermode")
Signed-off-by: James Hogan 
Cc: linux-mips@linux-mips.org
Cc:  # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/16656/
Signed-off-by: Ralf Baechle

format-security: move static strings to const

2017-05-09T00:15:14+00:00

While examining output from trial builds with -Wformat-security enabled,
many strings were found that should be defined as "const", or as a char
array instead of char pointer.  This makes some static analysis easier,
by producing fewer false positives.

As these are all trivial changes, it seemed best to put them all in a
single patch rather than chopping them up per maintainer.

Link: http://lkml.kernel.org/r/20170405214711.GA5711@beast
Signed-off-by: Kees Cook 
Acked-by: Jes Sorensen 	[runner.c]
Cc: Tony Lindgren 
Cc: Russell King 
Cc: "Maciej W. Rozycki" 
Cc: Ralf Baechle 
Cc: Arnd Bergmann 
Cc: Greg Kroah-Hartman 
Cc: "Rafael J. Wysocki" 
Cc: Viresh Kumar 
Cc: Daniel Vetter 
Cc: Jani Nikula 
Cc: Sean Paul 
Cc: David Airlie 
Cc: Yisen Zhuang 
Cc: Salil Mehta 
Cc: Thomas Bogendoerfer 
Cc: Jiri Slaby 
Cc: Patrice Chotard 
Cc: "David S. Miller" 
Cc: James Hogan 
Cc: Paul Burton 
Cc: Matt Redfearn 
Cc: Paolo Bonzini 
Cc: Ingo Molnar 
Cc: Rasmus Villemoes 
Cc: Mugunthan V N 
Cc: Felipe Balbi 
Cc: Jarod Wilson 
Cc: Florian Westphal 
Cc: Antonio Quartulli 
Cc: Dmitry Torokhov 
Cc: Kejian Yan 
Cc: Daode Huang 
Cc: Qianqian Xie 
Cc: Philippe Reynes 
Cc: Colin Ian King 
Cc: Eric Dumazet 
Cc: Christian Gromm 
Cc: Andrey Shvetsov 
Cc: Jason Litzinger 
Cc: WANG Cong 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3

2017-03-21T20:52:54+00:00

Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That
means: when a JTLB entry is replaced by hardware, there may be an old
valid entry exists in ITLB. So, a TLB miss exception may occur while
handle_ri_rdhwr() is running because it try to access EPC's content.
However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill
exception be treated as a TLB Invalid exception and tlbp may fail. In
this case, if FTLB (which is usually set-associative instead of set-
associative) is enabled, a tlbp failure will cause an invalid tlbwi,
which will hang the whole system.

This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use
it for Loongson-3. It try to solve the same problem described as below,
but more straightforwards.

https://patchwork.linux-mips.org/patch/12591/

I think Loongson-2 has the same problem, but it has no FTLB, so we just
keep it as is.

Signed-off-by: Huacai Chen 
Cc: Rui Wang 
Cc: John Crispin 
Cc: Steven J . Hill 
Cc: Fuxin Zhang 
Cc: Zhangjin Wu 
Cc: Huacai Chen 
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/15753/
Signed-off-by: Ralf Baechle