linux.git/arch/sh/kernel/cpu/sh2, branch v5.4.252

sh: j2: Use ioremap() to translate device tree address into kernel memory

2023-07-27T06:37:20+00:00

[ Upstream commit bc9d1f0cecd2407cfb2364a7d4be2f52d1d46a9d ]

Addresses the following warning when building j2_defconfig:

arch/sh/kernel/cpu/sh2/probe.c: In function 'scan_cache':
arch/sh/kernel/cpu/sh2/probe.c:24:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
   24 |  j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node);
      |

Fixes: 5a846abad07f ("sh: add support for J-Core J2 processor")
Reviewed-by: Geert Uytterhoeven 
Tested-by: Rob Landley 
Signed-off-by: John Paul Adrian Glaubitz 
Link: https://lore.kernel.org/r/20230503125746.331835-1-glaubitz@physik.fu-berlin.de
Signed-off-by: John Paul Adrian Glaubitz 
Signed-off-by: Sasha Levin

sh: sh2: convert to SPDX identifiers

2018-12-28T20:11:45+00:00

Update license to use SPDX-License-Identifier instead of verbose license
text.

Link: http://lkml.kernel.org/r/87efawcszk.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Kuninori Morimoto 
Reviewed-by: Simon Horman 
Cc: Rich Felker 
Cc: Yoshinori Sato 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

sh: fix build failure for J2 cpu with SMP disabled

2018-05-05T20:51:40+00:00

The sh asm/smp.h defines a fallback hard_smp_processor_id macro for
the !SMP case, but linux/smp.h never includes asm/smp.h in the !SMP
case.

Signed-off-by: Rich Felker

sh_eth: remove sh_eth_plat_data::edmac_endian

2018-01-08T19:10:33+00:00

Since the commit 888cc8c20cf ("sh_eth: remove EDMAC_BIG_ENDIAN") (geez,
I didn't realize that was 2 years ago!) the initializers in the SuperH
platform code for the 'sh_eth_plat_data::edmac_endian' stopped to matter,
so we can remove that field for good (not sure if  it  was ever useful --
SH7786 Ether has been reported  to have the same EDMAC descriptor/register
endiannes as configured for the SuperH CPU)...

Signed-off-by: Sergei Shtylyov 
Signed-off-by: David S. Miller

sh: Don't set the sh-sci pdata UPF_BOOT_AUTOCONF flags

2017-01-19T13:17:05+00:00

The flag is set by the driver internally, don't set it in platform data.

Signed-off-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Greg Kroah-Hartman

sh: Don't set sh-sci pdata scscr TE and RE bits

2017-01-19T13:17:04+00:00

The bits are set by the driver internally, don't set them in platform
data.

Signed-off-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Greg Kroah-Hartman

sh: add SMP support for J2

2016-08-05T03:29:39+00:00

Support is hooked up via a cpu start method specified in the device
tree, and also depends on DT nodes that describe the interfaces for
performing IPI and identifying which cpu execution is taking place on.
The currently used method is a form of spin table, where secondary
cpus are unblocked by writing to a special address.

Signed-off-by: Rich Felker

sh: SMP support for SH2 entry.S

2016-08-05T03:29:37+00:00

The SH2 version of entry.S uses global variables, which need to be
cpu-local in order to work with SMP. For ease of access from asm,
simply use arrays indexed by cpu number, and require the availability
of an address (mmio register or properly setup per-cpu memory) from
which the current cpu's index can be read.

Signed-off-by: Rich Felker

sh: add AT_HWCAP flag for J-Core cas.l instruction

2016-08-05T03:29:32+00:00

The J-Core cpu has, as an ISA extension, an atomic compare-and-swap
instruction cas.l which applications need to use (instead the imask or
gusa atomic models, which are fundamentally limited to UP) for
synchronization in order to be compatible with SMP systems. Provide a
hwcap flag so that it's possible to do runtime selection and support
both.

Signed-off-by: Rich Felker

sh: add support for J-Core J2 processor

2016-08-05T03:29:31+00:00

At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.

Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.

No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.

Signed-off-by: Rich Felker