<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/xtensa/kernel/asm-offsets.c, branch v3.18.22</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>xtensa: add support for TLS</title>
<updated>2013-02-24T03:35:57+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2013-02-24T03:35:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=c50842df47970eab459f13490c152aac85fc02f2'/>
<id>c50842df47970eab459f13490c152aac85fc02f2</id>
<content type='text'>
The Xtensa architecture provides a global register called THREADPTR
for the purpose of Thread Local Storage (TLS) support. This allows us
to use a fairly simple implementation, keeping the thread pointer in
the regset and simply saving and restoring it upon entering/exiting
the from user space.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Xtensa architecture provides a global register called THREADPTR
for the purpose of Thread Local Storage (TLS) support. This allows us
to use a fairly simple implementation, keeping the thread pointer in
the regset and simply saving and restoring it upon entering/exiting
the from user space.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: clean up files to make them code-style compliant</title>
<updated>2012-12-19T05:10:25+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2012-11-29T00:53:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=c4c4594b005d89b56964071bbbdeb07daac5bc76'/>
<id>c4c4594b005d89b56964071bbbdeb07daac5bc76</id>
<content type='text'>
Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: save and restore scompare1 SR on kernel entry</title>
<updated>2012-12-19T05:10:22+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2012-11-15T02:25:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=733536b865441d9bad02c4711a4372d48ce21e54'/>
<id>733536b865441d9bad02c4711a4372d48ce21e54</id>
<content type='text'>
Although scompare1 may be saved/restored by xchal_ncp_{load,store}
macros, explicit save/restore of registers manipulated by the kernel
itself is considered more correct.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Although scompare1 may be saved/restored by xchal_ncp_{load,store}
macros, explicit save/restore of registers manipulated by the kernel
itself is considered more correct.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: Shuffle include statements to fix linker script</title>
<updated>2010-05-02T08:05:13+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2010-05-02T08:05:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=4573e398d591a2fe6c600908578fd31401746529'/>
<id>4573e398d591a2fe6c600908578fd31401746529</id>
<content type='text'>
The linker script was including assembly macros from the coprocessor
header file that is not otherwise used by the script.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The linker script was including assembly macros from the coprocessor
header file that is not otherwise used by the script.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: use kbuild.h macros instead of defining them in asm-offsets.c</title>
<updated>2008-04-29T15:06:29+00:00</updated>
<author>
<name>Christoph Lameter</name>
<email>clameter@sgi.com</email>
</author>
<published>2008-04-29T08:04:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=0fcfbb1d317593d3d713a850bfdb310cc1585ae2'/>
<id>0fcfbb1d317593d3d713a850bfdb310cc1585ae2</id>
<content type='text'>
Signed-off-by: Christoph Lameter &lt;clameter@sgi.com&gt;
Cc: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Christoph Lameter &lt;clameter@sgi.com&gt;
Cc: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[XTENSA] Add support for configurable registers and coprocessors</title>
<updated>2008-02-14T01:41:43+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2008-02-12T21:17:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=c658eac628aa8df040dfe614556d95e6da3a9ffb'/>
<id>c658eac628aa8df040dfe614556d95e6da3a9ffb</id>
<content type='text'>
The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[XTENSA] Remove duplicate includes.</title>
<updated>2008-02-13T23:05:35+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2008-01-18T22:26:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=1e12e3919ea83ce28f8c017b83f68739485fef81'/>
<id>1e12e3919ea83ce28f8c017b83f68739485fef81</id>
<content type='text'>
Signed-off-by: Lucas Woods &lt;woodzy@gmail.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Christian Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Lucas Woods &lt;woodzy@gmail.com&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Christian Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[XTENSA] Add support for cache-aliasing</title>
<updated>2007-08-27T20:54:16+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2007-08-22T17:14:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=6656920b0b50beacb6cb64cf55273cbb686e436e'/>
<id>6656920b0b50beacb6cb64cf55273cbb686e436e</id>
<content type='text'>
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[XTENSA] Remove non-rt signal handling</title>
<updated>2007-06-01T00:49:32+00:00</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2007-06-01T00:49:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=29c4dfd92edc26c2cd2c0c64c9201d5b91d6418e'/>
<id>29c4dfd92edc26c2cd2c0c64c9201d5b91d6418e</id>
<content type='text'>
The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The non-rt signal handling was never really used, so we don't break
anything. This patch also cleans up the signal stack-frame to make
it independent from the processor configuration. It also improves
the method used for controlling single-stepping. We now save and
restore the 'icountlevel' register that controls single stepping
and set or clear the saved state to enable or disable it.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rename thread_info to stack</title>
<updated>2007-05-09T19:30:56+00:00</updated>
<author>
<name>Roman Zippel</name>
<email>zippel@linux-m68k.org</email>
</author>
<published>2007-05-09T09:35:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=f7e4217b007d1f73e7e3cf10ba4fea4a608c603f'/>
<id>f7e4217b007d1f73e7e3cf10ba4fea4a608c603f</id>
<content type='text'>
This finally renames the thread_info field in task structure to stack, so that
the assumptions about this field are gone and archs have more freedom about
placing the thread_info structure.

Nonbroken archs which have a proper thread pointer can do the access to both
current thread and task structure via a single pointer.

It'll allow for a few more cleanups of the fork code, from which e.g.  ia64
could benefit.

Signed-off-by: Roman Zippel &lt;zippel@linux-m68k.org&gt;
[akpm@linux-foundation.org: build fix]
Cc: Richard Henderson &lt;rth@twiddle.net&gt;
Cc: Ivan Kokshaysky &lt;ink@jurassic.park.msu.ru&gt;
Cc: Russell King &lt;rmk@arm.linux.org.uk&gt;
Cc: Ian Molton &lt;spyro@f2s.com&gt;
Cc: Haavard Skinnemoen &lt;hskinnemoen@atmel.com&gt;
Cc: Mikael Starvik &lt;starvik@axis.com&gt;
Cc: David Howells &lt;dhowells@redhat.com&gt;
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt;
Cc: "Luck, Tony" &lt;tony.luck@intel.com&gt;
Cc: Hirokazu Takata &lt;takata@linux-m32r.org&gt;
Cc: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Roman Zippel &lt;zippel@linux-m68k.org&gt;
Cc: Greg Ungerer &lt;gerg@uclinux.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paul Mackerras &lt;paulus@samba.org&gt;
Cc: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Cc: Heiko Carstens &lt;heiko.carstens@de.ibm.com&gt;
Cc: Martin Schwidefsky &lt;schwidefsky@de.ibm.com&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Kazumoto Kojima &lt;kkojima@rr.iij4u.or.jp&gt;
Cc: Richard Curnow &lt;rc@rc0.org.uk&gt;
Cc: William Lee Irwin III &lt;wli@holomorphy.com&gt;
Cc: "David S. Miller" &lt;davem@davemloft.net&gt;
Cc: Jeff Dike &lt;jdike@addtoit.com&gt;
Cc: Paolo 'Blaisorblade' Giarrusso &lt;blaisorblade@yahoo.it&gt;
Cc: Miles Bader &lt;uclinux-v850@lsi.nec.co.jp&gt;
Cc: Andi Kleen &lt;ak@muc.de&gt;
Cc: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This finally renames the thread_info field in task structure to stack, so that
the assumptions about this field are gone and archs have more freedom about
placing the thread_info structure.

Nonbroken archs which have a proper thread pointer can do the access to both
current thread and task structure via a single pointer.

It'll allow for a few more cleanups of the fork code, from which e.g.  ia64
could benefit.

Signed-off-by: Roman Zippel &lt;zippel@linux-m68k.org&gt;
[akpm@linux-foundation.org: build fix]
Cc: Richard Henderson &lt;rth@twiddle.net&gt;
Cc: Ivan Kokshaysky &lt;ink@jurassic.park.msu.ru&gt;
Cc: Russell King &lt;rmk@arm.linux.org.uk&gt;
Cc: Ian Molton &lt;spyro@f2s.com&gt;
Cc: Haavard Skinnemoen &lt;hskinnemoen@atmel.com&gt;
Cc: Mikael Starvik &lt;starvik@axis.com&gt;
Cc: David Howells &lt;dhowells@redhat.com&gt;
Cc: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt;
Cc: "Luck, Tony" &lt;tony.luck@intel.com&gt;
Cc: Hirokazu Takata &lt;takata@linux-m32r.org&gt;
Cc: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
Cc: Roman Zippel &lt;zippel@linux-m68k.org&gt;
Cc: Greg Ungerer &lt;gerg@uclinux.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Paul Mackerras &lt;paulus@samba.org&gt;
Cc: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Cc: Heiko Carstens &lt;heiko.carstens@de.ibm.com&gt;
Cc: Martin Schwidefsky &lt;schwidefsky@de.ibm.com&gt;
Cc: Paul Mundt &lt;lethal@linux-sh.org&gt;
Cc: Kazumoto Kojima &lt;kkojima@rr.iij4u.or.jp&gt;
Cc: Richard Curnow &lt;rc@rc0.org.uk&gt;
Cc: William Lee Irwin III &lt;wli@holomorphy.com&gt;
Cc: "David S. Miller" &lt;davem@davemloft.net&gt;
Cc: Jeff Dike &lt;jdike@addtoit.com&gt;
Cc: Paolo 'Blaisorblade' Giarrusso &lt;blaisorblade@yahoo.it&gt;
Cc: Miles Bader &lt;uclinux-v850@lsi.nec.co.jp&gt;
Cc: Andi Kleen &lt;ak@muc.de&gt;
Cc: Chris Zankel &lt;chris@zankel.net&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
