linux.git/arch/xtensa/kernel/asm-offsets.c, branch v4.4.183

xtensa: fix coprocessor context offset definitions

2018-12-13T08:21:26+00:00

commit 03bc996af0cc71c7f30c384d8ce7260172423b34 upstream.

Coprocessor context offsets are used by the assembly code that moves
coprocessor context between the individual fields of the
thread_info::xtregs_cp structure and coprocessor registers.
This fixes coprocessor context clobbering on flushing and reloading
during normal user code execution and user process debugging in the
presence of more than one coprocessor in the core configuration.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov 
Signed-off-by: Greg Kroah-Hartman

xtensa: Autogenerate offsets in struct thread_info

2015-04-12T19:03:29+00:00

Maintaining offsets by hand is no fun.

Reported-by: Guenter Roeck 
Signed-off-by: Richard Weinberger

xtensa: add support for TLS

2013-02-24T03:35:57+00:00

The Xtensa architecture provides a global register called THREADPTR
for the purpose of Thread Local Storage (TLS) support. This allows us
to use a fairly simple implementation, keeping the thread pointer in
the regset and simply saving and restoring it upon entering/exiting
the from user space.

Signed-off-by: Chris Zankel

xtensa: clean up files to make them code-style compliant

2012-12-19T05:10:25+00:00

Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel

xtensa: save and restore scompare1 SR on kernel entry

2012-12-19T05:10:22+00:00

Although scompare1 may be saved/restored by xchal_ncp_{load,store}
macros, explicit save/restore of registers manipulated by the kernel
itself is considered more correct.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: Shuffle include statements to fix linker script

2010-05-02T08:05:13+00:00

The linker script was including assembly macros from the coprocessor
header file that is not otherwise used by the script.

Signed-off-by: Chris Zankel

xtensa: use kbuild.h macros instead of defining them in asm-offsets.c

2008-04-29T15:06:29+00:00

Signed-off-by: Christoph Lameter 
Cc: Chris Zankel 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

[XTENSA] Add support for configurable registers and coprocessors

2008-02-14T01:41:43+00:00

The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.

This patch adds support for these additional states:

- save and restore registers that are used by the compiler upon
  interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf

Signed-off-by: Chris Zankel

[XTENSA] Remove duplicate includes.

2008-02-13T23:05:35+00:00

Signed-off-by: Lucas Woods 
Signed-off-by: Andrew Morton 
Signed-off-by: Christian Zankel

[XTENSA] Add support for cache-aliasing

2007-08-27T20:54:16+00:00

Add support for processors that have cache-aliasing issues, such as
the Stretch S5000 processor. Cache-aliasing means that the size of
the cache (for one way) is larger than the page size, thus, a page
can end up in several places in cache depending on the virtual to
physical translation. The method used here is to map a user page
temporarily through the auto-refill way 0 and of of the DTLB.
We probably will want to revisit this issue and use a better
approach with kmap/kunmap.

Signed-off-by: Chris Zankel