linux.git/arch/xtensa/kernel/entry.S, branch v3.13.6

xtensa: introduce spill_registers_kernel macro

2014-03-07T06:06:28+00:00

commit e2fd1374c705abe4661df3fb6fadb3879c7c1846 upstream.

Most in-kernel users want registers spilled on the kernel stack and
don't require PS.EXCM to be set. That means that they don't need fixup
routine and could reuse regular window overflow mechanism for that,
which makes spill routine very simple.

Suggested-by: Chris Zankel 
Signed-off-by: Max Filippov 
Signed-off-by: Greg Kroah-Hartman

xtensa: save current register frame in fast_syscall_spill_registers_fixup

2014-03-07T06:06:28+00:00

commit 3251f1e27a5a17f0efd436cfd1e7b9896cfab0a0 upstream.

We need it saved because it contains a3 where we track which register
windows we still need to spill, and fixup handler may call C exception
handlers. Also fix comments.

Signed-off-by: Max Filippov 
Signed-off-by: Greg Kroah-Hartman

xtensa: fix fast_syscall_spill_registers_fixup

2013-10-15T20:39:06+00:00

fast_syscall_spill_registers_fixup was not correctly updated by the
'keep a3 and excsave1 on entry to exception handlers' patch: it doesn't
preserve a3 that it gets on entry, breaking _spill_registers in case of
page fault on stack during register spilling, leading to unhandled
exception in kernel mode.

Preserve a3 by saving it in the original _spill_registers stack frame's
a3 during exception handling and restoring it afterwards.

Also fix comments and function bounds annotations.

Reported-by: Baruch Siach 
Signed-off-by: Max Filippov 
Tested-by: Baruch Siach 
Signed-off-by: Chris Zankel

xtensa: new fast_alloca handler

2013-09-06T16:48:12+00:00

Instead of emulating movsp instruction in the kernel use window
underflow handler to load missing register window and retry failed
movsp.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: keep a3 and excsave1 on entry to exception handlers

2013-09-06T16:47:41+00:00

Based on the SMP patch by Joe Taylor and subsequent fixes.
Preserve exception table pointer (normally stored in excsave1 SR) as it
cannot be easily restored in SMP environment.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: enable kernel preemption

2013-09-06T16:46:49+00:00

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: check thread flags atomically on return from user exception

2013-09-06T16:46:35+00:00

Check pending signals and rescheduling thread flags with interrupts
disabled, and don't enable them if no flags are set. Call
trace_hardirqs_on after thread flags handling, so that rescheduling is
done and hardirqs tracking flag is updated in the correct task context.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: check TLB sanity on return to userspace

2013-07-08T08:18:56+00:00

- check that user TLB mappings correspond to the current page table;
- check that TLB mapping VPN is in the kernel/user address range
  in accordance with its ASID.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: fix fast_store_prohibited _PAGE_WRITABLE_BIT test

2013-05-20T18:48:23+00:00

Before _PAGE_WRITABLE_BIT test fast_store_prohibited must make sure that
PTE is present. Otherwise 'writable' bit is undefined and may be reused
in the 'file offset' or 'swap type' PTE fields.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: disable IRQs while IRQ handler is running

2013-05-09T08:07:11+00:00

IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.

This was overlooked in the commit
  2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.

do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel