linux.git/arch/xtensa/kernel/head.S, branch v4.4.183

xtensa: SMP: fix secondary CPU initialization

2019-03-23T07:44:25+00:00

[ Upstream commit 32a7726c4f4aadfabdb82440d84f88a5a2c8fe13 ]

- add missing memory barriers to the secondary CPU synchronization spin
  loops; add comment to the matching memory barrier in the boot_secondary
  and __cpu_die functions;
- use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount
  instead of reading/writing them directly;
- re-initialize cpu_running every time before starting secondary CPU to
  flush possible previous CPU startup results.

Signed-off-by: Max Filippov 
Signed-off-by: Sasha Levin

xtensa: fix boot parameters address translation

2018-11-21T08:27:41+00:00

commit 40dc948f234b73497c3278875eb08a01d5854d3f upstream.

The bootloader may pass physical address of the boot parameters structure
to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in
the arch/xtensa/kernel/head.S is supposed to map that physical address to
the virtual address in the configured virtual memory layout.

This code haven't been updated when additional 256+256 and 512+512
memory layouts were introduced and it may produce wrong addresses when
used with these layouts.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov 
Signed-off-by: Greg Kroah-Hartman

xtensa: clear all DBREAKC registers on start

2016-04-12T16:08:55+00:00

commit 7de7ac785ae18a2cdc78d7560f48e3213d9ea0ab upstream.

There are XCHAL_NUM_DBREAK registers, clear them all.
This also fixes cryptic assembler error message with binutils 2.25 when
XCHAL_NUM_DBREAK is 0:

  as: out of memory allocating 18446744073709551575 bytes after a total
  of 495616 bytes

Signed-off-by: Max Filippov 
Signed-off-by: Greg Kroah-Hartman

xtensa: fixes for configs without loop option

2015-11-02T15:02:47+00:00

Build-time fixes:
- make lbeg/lend/lcount save/restore conditional on kernel entry;
- don't clear lcount in platform_restart functions unconditionally.

Run-time fixes:
- use correct end of range register in __endla paired with __loopt, not
  the unused temporary register. This fixes .bss zero-initialization.
  Update comments in asmmacro.h;
- don't clobber a10 in the usercopy that leads to access to unmapped
  memory.

Cc: 
Signed-off-by: Max Filippov

xtensa: move vecbase SR initialization to _startup

2014-10-21T09:28:55+00:00

Instead of initializing vecbase in initialize_mmu macro, which may be
expanded either in Image.elf reset vector hadler or in the kernel
head.S, both times only when CONFIG_MMU is enabled, do this
initialization once in _startup function.

Signed-off-by: Max Filippov

xtensa: implement CPU hotplug

2014-01-14T18:19:59+00:00

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add SMP support

2014-01-14T18:19:58+00:00

This is largely based on SMP code from the xtensa-2.6.29-smp tree by
Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly
other Tensilica folks).

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: adjust boot parameters address when INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is selected

2013-07-08T08:18:56+00:00

The virtual address of boot parameters chain is passed to the kernel via
a2 register. Adjust it in case it is remapped during MMUv3 -> MMUv2
mapping change, i.e. when it is in the first 128M.

Also fix interpretation of initrd and FDT addresses passed in the boot
parameters: these are physical addresses.

Cc: stable@vger.kernel.org
Reported-by: Baruch Siach 
Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: add MMU v3 support

2013-05-09T08:07:09+00:00

MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:

Way 6 (512 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0x00000000  0x00000000  0x01  0x03 RWX Bypass
        0x20000000  0x20000000  0x01  0x03 RWX Bypass
        0x40000000  0x40000000  0x01  0x03 RWX Bypass
        0x60000000  0x60000000  0x01  0x03 RWX Bypass
        0x80000000  0x80000000  0x01  0x03 RWX Bypass
        0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
        0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
        0xe0000000  0xe0000000  0x01  0x03 RWX Bypass

This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:

Way 5 (128 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xd0000000  0x00000000  0x01  0x07 RWX WB
        0xd8000000  0x00000000  0x01  0x03 RWX Bypass
Way 6 (256 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xe0000000  0xf0000000  0x01  0x07 RWX WB
        0xf0000000  0xf0000000  0x01  0x03 RWX Bypass

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel

xtensa: fix ibreakenable register update

2013-05-09T08:07:09+00:00

Only set the register when there is at least one ibreak register,
otherwise the build fails:
	arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
	for 'wsr' instruction
	arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
	'ibreakenable' for 'wsr' instruction

Signed-off-by: Max Filippov 
Signed-off-by: Chris Zankel