<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/xtensa/kernel/pci.c, branch v4.4.288</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>PCI: Revert "PCI: Call pci_read_bridge_bases() from core instead of arch code"</title>
<updated>2015-09-15T18:18:04+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2015-09-15T18:18:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=237865f195f6b10e4724ce49eeb3972641da882a'/>
<id>237865f195f6b10e4724ce49eeb3972641da882a</id>
<content type='text'>
Revert dff22d2054b5 ("PCI: Call pci_read_bridge_bases() from core instead
of arch code").

Reading PCI bridge windows is not arch-specific in itself, but there is PCI
core code that doesn't work correctly if we read them too early.  For
example, Hannes found this case on an ARM Freescale i.mx6 board:

  pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
  pci 0000:00:00.0: PCI bridge to [bus 01-ff]
  pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window)
  pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000]
  pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000]
  pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100]

The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs
0x204100 of space, and mem windows are megabyte-aligned.

Bus sizing can increase a bridge window size, but never *decrease* it (see
d65245c3297a ("PCI: don't shrink bridge resources")).  Prior to
dff22d2054b5, ARM didn't read bridge windows at all, so the "original size"
was zero, and we assigned a 3MB window.

After dff22d2054b5, we read the bridge windows before sizing the bus.  The
firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since
we never decrease the size, we kept 16MB even though we only needed 3MB.
But 16MB doesn't fit in the host bridge aperture, so we failed to assign
space for the window and the downstream devices.

I think this is a defect in the PCI core: we shouldn't rely on the firmware
to assign sensible windows.

Ray reported a similar problem, also on ARM, with Broadcom iProc.

Issues like this are too hard to fix right now, so revert dff22d2054b5.

Reported-by: Hannes &lt;oe5hpm@gmail.com&gt;
Reported-by: Ray Jui &lt;rjui@broadcom.com&gt;
Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com
Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.com
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Yinghai Lu &lt;yinghai@kernel.org&gt;
Acked-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Revert dff22d2054b5 ("PCI: Call pci_read_bridge_bases() from core instead
of arch code").

Reading PCI bridge windows is not arch-specific in itself, but there is PCI
core code that doesn't work correctly if we read them too early.  For
example, Hannes found this case on an ARM Freescale i.mx6 board:

  pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
  pci 0000:00:00.0: PCI bridge to [bus 01-ff]
  pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window)
  pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000]
  pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000]
  pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100]

The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs
0x204100 of space, and mem windows are megabyte-aligned.

Bus sizing can increase a bridge window size, but never *decrease* it (see
d65245c3297a ("PCI: don't shrink bridge resources")).  Prior to
dff22d2054b5, ARM didn't read bridge windows at all, so the "original size"
was zero, and we assigned a 3MB window.

After dff22d2054b5, we read the bridge windows before sizing the bus.  The
firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since
we never decrease the size, we kept 16MB even though we only needed 3MB.
But 16MB doesn't fit in the host bridge aperture, so we failed to assign
space for the window and the downstream devices.

I think this is a defect in the PCI core: we shouldn't rely on the firmware
to assign sensible windows.

Ray reported a similar problem, also on ARM, with Broadcom iProc.

Issues like this are too hard to fix right now, so revert dff22d2054b5.

Reported-by: Hannes &lt;oe5hpm@gmail.com&gt;
Reported-by: Ray Jui &lt;rjui@broadcom.com&gt;
Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com
Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.com
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Yinghai Lu &lt;yinghai@kernel.org&gt;
Acked-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>PCI: Call pci_read_bridge_bases() from core instead of arch code</title>
<updated>2015-07-23T15:13:29+00:00</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lorenzo.pieralisi@arm.com</email>
</author>
<published>2015-07-09T10:59:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=dff22d2054b5dbb1889f20c03959dd0c494fab8c'/>
<id>dff22d2054b5dbb1889f20c03959dd0c494fab8c</id>
<content type='text'>
When we scan a PCI bus, we read PCI-PCI bridge window registers with
pci_read_bridge_bases() so we can validate the resource hierarchy.  Most
architectures call pci_read_bridge_bases() from pcibios_fixup_bus(), but
PCI-PCI bridges are not arch-specific, so this doesn't need to be in
arch-specific code.

Call pci_read_bridge_bases() directly from the PCI core instead of from
arch code.

For alpha and mips, we now call pci_read_bridge_bases() always; previously
we only called it if PCI_PROBE_ONLY was set.

[bhelgaas: changelog]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Ralf Baechle &lt;ralf@linux-mips.org&gt;
CC: James E.J. Bottomley &lt;jejb@parisc-linux.org&gt;
CC: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
CC: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Richard Henderson &lt;rth@twiddle.net&gt;
CC: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
CC: David Howells &lt;dhowells@redhat.com&gt;
CC: Russell King &lt;linux@arm.linux.org.uk&gt;
CC: Tony Luck &lt;tony.luck@intel.com&gt;
CC: David S. Miller &lt;davem@davemloft.net&gt;
CC: Ingo Molnar &lt;mingo@redhat.com&gt;
CC: Guenter Roeck &lt;linux@roeck-us.net&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
CC: Chris Zankel &lt;chris@zankel.net&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
When we scan a PCI bus, we read PCI-PCI bridge window registers with
pci_read_bridge_bases() so we can validate the resource hierarchy.  Most
architectures call pci_read_bridge_bases() from pcibios_fixup_bus(), but
PCI-PCI bridges are not arch-specific, so this doesn't need to be in
arch-specific code.

Call pci_read_bridge_bases() directly from the PCI core instead of from
arch code.

For alpha and mips, we now call pci_read_bridge_bases() always; previously
we only called it if PCI_PROBE_ONLY was set.

[bhelgaas: changelog]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Ralf Baechle &lt;ralf@linux-mips.org&gt;
CC: James E.J. Bottomley &lt;jejb@parisc-linux.org&gt;
CC: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
CC: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Richard Henderson &lt;rth@twiddle.net&gt;
CC: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
CC: David Howells &lt;dhowells@redhat.com&gt;
CC: Russell King &lt;linux@arm.linux.org.uk&gt;
CC: Tony Luck &lt;tony.luck@intel.com&gt;
CC: David S. Miller &lt;davem@davemloft.net&gt;
CC: Ingo Molnar &lt;mingo@redhat.com&gt;
CC: Guenter Roeck &lt;linux@roeck-us.net&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
CC: Chris Zankel &lt;chris@zankel.net&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>PCI: Assign resources before drivers claim devices (pci_scan_root_bus())</title>
<updated>2015-03-19T15:17:13+00:00</updated>
<author>
<name>Yijing Wang</name>
<email>wangyijing@huawei.com</email>
</author>
<published>2015-03-16T03:18:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=b97ea289cf6aff8d4cbcefe2b707bb9b00a73c73'/>
<id>b97ea289cf6aff8d4cbcefe2b707bb9b00a73c73</id>
<content type='text'>
Previously, pci_scan_root_bus() created a root PCI bus, enumerated the
devices on it, and called pci_bus_add_devices(), which made the devices
available for drivers to claim them.

Most callers assigned resources to devices after pci_scan_root_bus()
returns, which may be after drivers have claimed the devices.  This is
incorrect; the PCI core should not change device resources while a driver
is managing the device.

Remove pci_bus_add_devices() from pci_scan_root_bus() and do it after any
resource assignment in the callers.

Note that ARM's pci_common_init_dev() already called pci_bus_add_devices()
after pci_scan_root_bus(), so we only need to remove the first call:

  pci_common_init_dev
    pcibios_init_hw
      pci_scan_root_bus
        pci_bus_add_devices        # first call
    pci_bus_assign_resources
    pci_bus_add_devices            # second call

[bhelgaas: changelog, drop "root_bus" var in alpha common_init_pci(),
return failure earlier in mn10300, add "return" in x86 pcibios_scan_root(),
return early if xtensa platform_pcibios_fixup() fails]
Signed-off-by: Yijing Wang &lt;wangyijing@huawei.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Richard Henderson &lt;rth@twiddle.net&gt;
CC: Ivan Kokshaysky &lt;ink@jurassic.park.msu.ru&gt;
CC: Matt Turner &lt;mattst88@gmail.com&gt;
CC: David Howells &lt;dhowells@redhat.com&gt;
CC: Tony Luck &lt;tony.luck@intel.com&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
CC: Ralf Baechle &lt;ralf@linux-mips.org&gt;
CC: Koichi Yasutake &lt;yasutake.koichi@jp.panasonic.com&gt;
CC: Sebastian Ott &lt;sebott@linux.vnet.ibm.com&gt;
CC: "David S. Miller" &lt;davem@davemloft.net&gt;
CC: Chris Metcalf &lt;cmetcalf@ezchip.com&gt;
CC: Chris Zankel &lt;chris@zankel.net&gt;
CC: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Previously, pci_scan_root_bus() created a root PCI bus, enumerated the
devices on it, and called pci_bus_add_devices(), which made the devices
available for drivers to claim them.

Most callers assigned resources to devices after pci_scan_root_bus()
returns, which may be after drivers have claimed the devices.  This is
incorrect; the PCI core should not change device resources while a driver
is managing the device.

Remove pci_bus_add_devices() from pci_scan_root_bus() and do it after any
resource assignment in the callers.

Note that ARM's pci_common_init_dev() already called pci_bus_add_devices()
after pci_scan_root_bus(), so we only need to remove the first call:

  pci_common_init_dev
    pcibios_init_hw
      pci_scan_root_bus
        pci_bus_add_devices        # first call
    pci_bus_assign_resources
    pci_bus_add_devices            # second call

[bhelgaas: changelog, drop "root_bus" var in alpha common_init_pci(),
return failure earlier in mn10300, add "return" in x86 pcibios_scan_root(),
return early if xtensa platform_pcibios_fixup() fails]
Signed-off-by: Yijing Wang &lt;wangyijing@huawei.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
CC: Richard Henderson &lt;rth@twiddle.net&gt;
CC: Ivan Kokshaysky &lt;ink@jurassic.park.msu.ru&gt;
CC: Matt Turner &lt;mattst88@gmail.com&gt;
CC: David Howells &lt;dhowells@redhat.com&gt;
CC: Tony Luck &lt;tony.luck@intel.com&gt;
CC: Michal Simek &lt;monstr@monstr.eu&gt;
CC: Ralf Baechle &lt;ralf@linux-mips.org&gt;
CC: Koichi Yasutake &lt;yasutake.koichi@jp.panasonic.com&gt;
CC: Sebastian Ott &lt;sebott@linux.vnet.ibm.com&gt;
CC: "David S. Miller" &lt;davem@davemloft.net&gt;
CC: Chris Metcalf &lt;cmetcalf@ezchip.com&gt;
CC: Chris Zankel &lt;chris@zankel.net&gt;
CC: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
CC: Thomas Gleixner &lt;tglx@linutronix.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa: fix section mismatch in pcibios_fixup_bus</title>
<updated>2013-06-05T17:14:22+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2013-05-27T15:45:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=fd95ee7380ae973c6f11b897af6ef9d253a1df9e'/>
<id>fd95ee7380ae973c6f11b897af6ef9d253a1df9e</id>
<content type='text'>
Remove __init annotation from pcibios_fixup_bus as is called from
pci_scan_child_bus which is not __init.

Also fix a couple of minor build warnings.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove __init annotation from pcibios_fixup_bus as is called from
pci_scan_child_bus which is not __init.

Also fix a couple of minor build warnings.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'xtensa-next-20121008' of git://github.com/czankel/xtensa-linux</title>
<updated>2012-10-09T07:11:46+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2012-10-09T07:11:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=1ea4f4f8405cc1ceec23f2d261bc3775785e6712'/>
<id>1ea4f4f8405cc1ceec23f2d261bc3775785e6712</id>
<content type='text'>
Pull Xtensa patchset from Chris Zankel:
 "The Xtensa tree has been broken for some time now, and this patchset
  brings it back to life.  It has been part of the linux-next tree for
  some time.

  Most changes are inside the xtensa subdirectory; the other changes
  mostly add another rule to already existing #ifdefs to exclude Xtensa,
  where required.  The only 'common' change is to add two more sections
  ('.xt.prop' and '.xt.lit') to the white list in modpost."

* tag 'xtensa-next-20121008' of git://github.com/czankel/xtensa-linux: (27 commits)
  xtensa: Setup CROSS_COMPILE at the top
  xtensa: drop CONFIG_EMBEDDED_RAMDISK
  xtensa: fix TIOCGSERIAL and TIOCSSERIAL definitions
  xtensa: provide dummy gcc intrinsics
  xtensa: add missing symbol exports
  parport: disable for xtensa arch
  xtensa: rename MISC SR definition to avoid name clashes
  hisax: disable build for big-endian xtensa
  xtensa: fix CODA build
  xtensa: fix parallel make
  xtensa: ISS: drop unused io.c
  xtensa: ISS: exit simulator in case of halt or poweroff
  xtensa: ISS: change keyboard polling rate
  xtensa: ISS: add platform_pcibios_init
  xtensa: ISS: add dummy serial.h for ISS platform
  xtensa: change default platform clock frequency to 10MHz
  xtensa: add ARCH_WANT_OPTIONAL_GPIOLIB to xtensa config
  xtensa: set NO_IOPORT to 'n' by default
  xtensa: adopt generic io routines
  xtensa: fix ioremap
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull Xtensa patchset from Chris Zankel:
 "The Xtensa tree has been broken for some time now, and this patchset
  brings it back to life.  It has been part of the linux-next tree for
  some time.

  Most changes are inside the xtensa subdirectory; the other changes
  mostly add another rule to already existing #ifdefs to exclude Xtensa,
  where required.  The only 'common' change is to add two more sections
  ('.xt.prop' and '.xt.lit') to the white list in modpost."

* tag 'xtensa-next-20121008' of git://github.com/czankel/xtensa-linux: (27 commits)
  xtensa: Setup CROSS_COMPILE at the top
  xtensa: drop CONFIG_EMBEDDED_RAMDISK
  xtensa: fix TIOCGSERIAL and TIOCSSERIAL definitions
  xtensa: provide dummy gcc intrinsics
  xtensa: add missing symbol exports
  parport: disable for xtensa arch
  xtensa: rename MISC SR definition to avoid name clashes
  hisax: disable build for big-endian xtensa
  xtensa: fix CODA build
  xtensa: fix parallel make
  xtensa: ISS: drop unused io.c
  xtensa: ISS: exit simulator in case of halt or poweroff
  xtensa: ISS: change keyboard polling rate
  xtensa: ISS: add platform_pcibios_init
  xtensa: ISS: add dummy serial.h for ISS platform
  xtensa: change default platform clock frequency to 10MHz
  xtensa: add ARCH_WANT_OPTIONAL_GPIOLIB to xtensa config
  xtensa: set NO_IOPORT to 'n' by default
  xtensa: adopt generic io routines
  xtensa: fix ioremap
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa/PCI: fix WT caching attribute</title>
<updated>2012-10-03T22:11:13+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2012-09-17T01:44:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=2e6ee5ec88dd9d4d4e934709200259538160039d'/>
<id>2e6ee5ec88dd9d4d4e934709200259538160039d</id>
<content type='text'>
Fix caching attributes setup providing correct _PAGE_CA_* names.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix caching attributes setup providing correct _PAGE_CA_* names.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI: Provide a default pcibios_update_irq()</title>
<updated>2012-09-18T23:28:21+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@avionic-design.de</email>
</author>
<published>2012-09-17T11:22:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=8885b7b637fa9aca7e1b00581a0173c6956966d3'/>
<id>8885b7b637fa9aca7e1b00581a0173c6956966d3</id>
<content type='text'>
Most architectures implement this in exactly the same way. Instead of
having each architecture duplicate this function, provide a single
implementation in the core and make it a weak symbol so that it can be
overridden on architectures where it is required.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Most architectures implement this in exactly the same way. Instead of
having each architecture duplicate this function, provide a single
implementation in the core and make it a weak symbol so that it can be
overridden on architectures where it is required.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>PCI: Discard __init annotations for pci_fixup_irqs() and related functions</title>
<updated>2012-09-18T23:22:25+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@avionic-design.de</email>
</author>
<published>2012-09-17T11:22:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=3ddbebf878ac8d958bb34e87a742a6b3adc283a3'/>
<id>3ddbebf878ac8d958bb34e87a742a6b3adc283a3</id>
<content type='text'>
Remove the __init annotations in order to keep pci_fixup_irqs() around
after init (e.g. for hotplug). This requires the same change for the
implementation of pcibios_update_irq() on all architectures. While at
it, all __devinit annotations are removed as well, since they will be
useless now that HOTPLUG is always on.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove the __init annotations in order to keep pci_fixup_irqs() around
after init (e.g. for hotplug). This requires the same change for the
implementation of pcibios_update_irq() on all architectures. While at
it, all __devinit annotations are removed as well, since they will be
useless now that HOTPLUG is always on.

Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'pci/myron-pcibios_setup' into next</title>
<updated>2012-07-05T21:31:05+00:00</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2012-07-05T21:31:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=85a00dd391d2de1e177c5ad8db5672428934ac20'/>
<id>85a00dd391d2de1e177c5ad8db5672428934ac20</id>
<content type='text'>
* pci/myron-pcibios_setup:
  xtensa/PCI: factor out pcibios_setup()
  x86/PCI: adjust section annotations for pcibios_setup()
  unicore32/PCI: adjust section annotations for pcibios_setup()
  tile/PCI: factor out pcibios_setup()
  sparc/PCI: factor out pcibios_setup()
  sh/PCI: adjust section annotations for pcibios_setup()
  sh/PCI: factor out pcibios_setup()
  powerpc/PCI: factor out pcibios_setup()
  parisc/PCI: factor out pcibios_setup()
  MIPS/PCI: adjust section annotations for pcibios_setup()
  MIPS/PCI: factor out pcibios_setup()
  microblaze/PCI: factor out pcibios_setup()
  ia64/PCI: factor out pcibios_setup()
  cris/PCI: factor out pcibios_setup()
  alpha/PCI: factor out pcibios_setup()
  PCI: pull pcibios_setup() up into core
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* pci/myron-pcibios_setup:
  xtensa/PCI: factor out pcibios_setup()
  x86/PCI: adjust section annotations for pcibios_setup()
  unicore32/PCI: adjust section annotations for pcibios_setup()
  tile/PCI: factor out pcibios_setup()
  sparc/PCI: factor out pcibios_setup()
  sh/PCI: adjust section annotations for pcibios_setup()
  sh/PCI: factor out pcibios_setup()
  powerpc/PCI: factor out pcibios_setup()
  parisc/PCI: factor out pcibios_setup()
  MIPS/PCI: adjust section annotations for pcibios_setup()
  MIPS/PCI: factor out pcibios_setup()
  microblaze/PCI: factor out pcibios_setup()
  ia64/PCI: factor out pcibios_setup()
  cris/PCI: factor out pcibios_setup()
  alpha/PCI: factor out pcibios_setup()
  PCI: pull pcibios_setup() up into core
</pre>
</div>
</content>
</entry>
<entry>
<title>xtensa/PCI: factor out pcibios_setup()</title>
<updated>2012-07-05T21:09:14+00:00</updated>
<author>
<name>Myron Stowe</name>
<email>myron.stowe@redhat.com</email>
</author>
<published>2012-06-26T03:32:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=29e8d7bff2f52dd5464a9fb24ece608bbf8fd5ae'/>
<id>29e8d7bff2f52dd5464a9fb24ece608bbf8fd5ae</id>
<content type='text'>
The PCI core provides a generic pcibios_setup() routine.  Drop this
architecture-specific version in favor of that.

Signed-off-by: Myron Stowe &lt;myron.stowe@redhat.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The PCI core provides a generic pcibios_setup() routine.  Drop this
architecture-specific version in favor of that.

Signed-off-by: Myron Stowe &lt;myron.stowe@redhat.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</pre>
</div>
</content>
</entry>
</feed>
