linux.git/drivers/clk/imx, branch v5.4.243

clk: imx: replace osc_hdmi with dummy

2023-01-18T10:41:06+00:00

[ Upstream commit e7fa365ff66f16772dc06b480cd78f858d10856b ]

There is no occurrence of the hdmi oscillator in the reference manual
(document IMX8MNRM Rev 2, 07/2022). Further, if we consider the indexes
76-81 and 134 of the "Clock Root" table of chapter 5 of the RM, there is
no entry for the source select bits 101b, which is the setting referenced
by "osc_hdmi".
Fix by renaming "osc_hdmi" with "dummy", a clock which has already been
used for missing source select bits.

Tested on the BSH SystemMaster (SMM) S2 board.

Fixes: 96d6392b54dbb ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Dario Binacchi 
Acked-by: Marco Felsch 
Signed-off-by: Abel Vesa 
Link: https://lore.kernel.org/r/20221117113637.1978703-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Sasha Levin

clk: imx8mn: correct the usb1_ctrl parent to be usb_bus

2023-01-18T10:41:05+00:00

[ Upstream commit 134d43bb1ff09a696996f16ed8b28d404b770c8a ]

Per latest imx8mn datasheet of CCM, the parent of usb1_ctrl_root_clk
should be usb_bus.

Signed-off-by: Li Jun 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks

2022-10-05T08:37:45+00:00

[ Upstream commit b1ff1bfe81e763420afd5f3f25f0b3cbfd97055c ]

There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag
should not be used. For instance, the default parent clock for QSPI is
pll2_bus, which is also the parent clock for quite a few modules, such
as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system
hang due to pll2_bus rate changed.

Fixes: f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API")
Signed-off-by: Han Xu 
Link: https://lore.kernel.org/r/20220915150959.3646702-1-han.xu@nxp.com
Tested-by: Fabio Estevam 
Reviewed-by: Abel Vesa 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: imx7d: Remove audio_mclk_root_clk

2022-04-15T12:18:18+00:00

[ Upstream commit eccac77ede3946c90143447cdc785dc16aec4b24 ]

The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790),
but according to the reference manual, there is no such gate. The
CCGR121 belongs to ECSPI2 and it is not shared.

Fixes: 8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support")
Reported-by: David Wolfe 
Signed-off-by: Abel Vesa 
Reviewed-by: Peng Fan 
Link: https://lore.kernel.org/r/20220127141052.1900174-2-abel.vesa@nxp.com
Signed-off-by: Sasha Levin

clk: imx8mn: Fix imx8mn_clko1_sels

2022-01-27T08:19:38+00:00

[ Upstream commit 570727e9acfac1c2330a01dd5e1272e9c3acec08 ]

When attempting to use sys_pll1_80m as the parent for clko1, the
system hangs.  This is due to the fact that the source select
for sys_pll1_80m was incorrectly pointing to m7_alt_pll_clk, which
doesn't yet exist.

According to Rev 3 of the TRM, The imx8mn_clko1_sels also incorrectly
references an osc_27m which does not exist, nor does an entry for
source select bits 010b.  Fix both by inserting a dummy clock into
the missing space in the table and renaming the incorrectly name clock
with dummy.

Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Adam Ford 
Reviewed-by: Fabio Estevam 
Link: https://lore.kernel.org/r/20211117133202.775633-1-aford173@gmail.com
Signed-off-by: Abel Vesa 
Signed-off-by: Sasha Levin

clk: imx: imx6ul: Move csi_sel mux to correct base register

2021-11-26T09:47:15+00:00

[ Upstream commit 2f9d61869640f732599ec36b984c2b5c46067519 ]

The csi_sel mux register is located in the CCM register base and not the
CCM_ANALOG register base. So move it to the correct position in code.

Otherwise changing the parent of the csi clock can lead to a complete
system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely
modified.

Also remove the SET_RATE_PARENT flag since one possible supply for the
csi_sel mux is the system PLL which we don't want to modify.

Signed-off-by: Stefan Riedmueller 
Reviewed-by: Abel Vesa 
Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de
Signed-off-by: Abel Vesa 
Signed-off-by: Sasha Levin

clk: imx8mq: Fix usdhc parents order

2020-10-29T08:57:56+00:00

[ Upstream commit b159c63d82ff8ffddc6c6f0eb881b113b36ecad7 ]

According to the latest RM (see Table 5-1. Clock Root Table),
both usdhc root clocks have the parent order as follows:

000 - 25M_REF_CLK
001 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
101 - SYSTEM_PLL1_DIV3
110 - AUDIO_PLL2_CLK
111 - SYSTEM_PLL1_DIV8

So the audio_pll2_out and sys3_pll_out have to be swapped.

Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa 
Reported-by: Cosmin Stefan Stoica 
Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com
Reviewed-by: Fabio Estevam 
Signed-off-by: Stephen Boyd 
Signed-off-by: Sasha Levin

clk: imx: Fix division by zero warning on pfdv2

2020-10-01T11:17:40+00:00

[ Upstream commit 28b2f82e0383e27476be8a5e13d2aea07ebeb275 ]

Fix below division by zero warning:

[    3.176443] Division by zero in kernel.
[    3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124
[    3.191817] Hardware name: Freescale i.MX7ULP (Device Tree)
[    3.197821] Workqueue: events dbs_work_handler
[    3.202849] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    3.211058] [] (show_stack) from [] (dump_stack+0xd8/0x110)
[    3.218820] [] (dump_stack) from [] (Ldiv0_64+0x8/0x18)
[    3.226263] [] (Ldiv0_64) from [] (clk_pfdv2_set_rate+0x54/0xac)
[    3.234487] [] (clk_pfdv2_set_rate) from [] (clk_change_rate+0x1a4/0x698)
[    3.243468] [] (clk_change_rate) from [] (clk_change_rate+0x280/0x698)
[    3.252180] [] (clk_change_rate) from [] (clk_core_set_rate_nolock+0x1a0/0x278)
[    3.261679] [] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x30/0x64)
[    3.270743] [] (clk_set_rate) from [] (imx7ulp_set_target+0x184/0x2a4)
[    3.279501] [] (imx7ulp_set_target) from [] (__cpufreq_driver_target+0x188/0x514)
[    3.289196] [] (__cpufreq_driver_target) from [] (od_dbs_update+0x130/0x15c)
[    3.298438] [] (od_dbs_update) from [] (dbs_work_handler+0x2c/0x5c)
[    3.306914] [] (dbs_work_handler) from [] (process_one_work+0x2ac/0x704)
[    3.315826] [] (process_one_work) from [] (worker_thread+0x2c/0x574)
[    3.324404] [] (worker_thread) from [] (kthread+0x134/0x148)
[    3.332278] [] (kthread) from [] (ret_from_fork+0x14/0x20)
[    3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8)
[    3.345314] 5fa0:                                     00000000 00000000 00000000 00000000
[    3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[    3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000

Signed-off-by: Anson Huang 
Signed-off-by: Peng Fan 
Signed-off-by: Shawn Guo 
Signed-off-by: Sasha Levin

clk: imx: Align imx sc clock parent msg structs to 4

2020-04-02T13:11:02+00:00

commit 8400ab8896324641243b57fc49b448023c07409a upstream.

The imx SC api strongly assumes that messages are composed out of
4-bytes words but some of our message structs have odd sizeofs.

This produces many oopses with CONFIG_KASAN=y.

Fix by marking with __aligned(4).

Fixes: 666aed2d13ee ("clk: imx: scu: add set parent support")
Signed-off-by: Leonard Crestez 
Link: https://lkml.kernel.org/r/aad021e432b3062c142973d09b766656eec18fde.1582216144.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman

clk: imx: Align imx sc clock msg structs to 4

2020-04-02T13:11:01+00:00

commit a0ae04a25650fd51b7106e742d27333e502173c6 upstream.

The imx SC api strongly assumes that messages are composed out of
4-bytes words but some of our message structs have odd sizeofs.

This produces many oopses with CONFIG_KASAN=y.

Fix by marking with __aligned(4).

Fixes: fe37b4820417 ("clk: imx: add scu clock common part")
Signed-off-by: Leonard Crestez 
Link: https://lkml.kernel.org/r/10e97a04980d933b2cfecb6b124bf9046b6e4f16.1582216144.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd 
Signed-off-by: Greg Kroah-Hartman