linux.git/drivers/clocksource, branch v6.0.6

clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probe

2022-10-21T10:39:00+00:00

[ Upstream commit 0e2c8e6d769bcdc4f6634a02c545356282275e68 ]

Add platform_device_put() to make sure to free the platform
device in the event platform_device_add() fails.

Fixes: 5184f4bf151b ("clocksource/drivers/timer-gxp: Add HPE GXP Timer")
Signed-off-by: Lin Yujun 
Link: https://lore.kernel.org/r/20220914033018.97484-1-linyujun809@huawei.com
Signed-off-by: Daniel Lezcano 
Signed-off-by: Sasha Levin

clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921

2022-10-21T10:38:59+00:00

[ Upstream commit 6c3b62d93e195f78c1437c8fa7581e9b2f00886e ]

The commit a38b71b0833e ("clocksource/drivers/arm_arch_timer:
Move system register timer programming over to CVAL") moves the
programming of the timers from the countdown timer (TVAL) over
to the comparator (CVAL). This makes it necessary to read the
counter when programming next event. However, the workaround of
Cortex-A73 erratum 858921 does not set the corresponding
set_next_event_phys and set_next_event_virt.

Add the appropriate hooks to apply the erratum mitigation when
programming the next timer event.

Fixes: a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL")
Signed-off-by: Kunkun Jiang 
Acked-by: Marc Zyngier 
Reviewed-by: Oliver Upton 
Link: https://lore.kernel.org/r/20220914061424.1260-1-jiangkunkun@huawei.com
Signed-off-by: Daniel Lezcano 
Signed-off-by: Sasha Levin

clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

2022-10-21T10:37:42+00:00

commit af246cc6d0ed11318223606128bb0b09866c4c08 upstream.

CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f883a7',
so fix them according to the Arm ARM DDI 0487I.a, Table I2-4
"CNTBaseN memory map" as follows:

Offset    Register      Type Description
0x000     CNTPCT[31:0]  RO   Physical Count register.
0x004     CNTPCT[63:32] RO
0x008     CNTVCT[31:0]  RO   Virtual Count register.
0x00C     CNTVCT[63:32] RO

Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: stable@vger.kernel.org
Cc: Daniel Lezcano 
Cc: Thomas Gleixner 
Cc: Marc Zyngier 
Cc: Mark Rutland 
Acked-by: Marc Zyngier 
Signed-off-by: Yang Guo 
Signed-off-by: Shaokun Zhang 
Link: https://lore.kernel.org/r/20220927033221.49589-1-zhangshaokun@hisilicon.com
Signed-off-by: Daniel Lezcano 
Signed-off-by: Greg Kroah-Hartman

RISC-V: Add Sstc extension support

2022-08-11T21:41:52+00:00

This series implements Sstc extension support which was ratified
recently.  Before the Sstc extension, an SBI call is necessary to
generate timer interrupts as only M-mode have access to the timecompare
registers. Thus, there is significant latency to generate timer
interrupts at kernel.  For virtualized enviornments, its even worse as
the KVM handles the SBI call and uses a software timer to emulate the
timecomapre register.

Sstc extension solves both these problems by defining a
stimecmp/vstimecmp at supervisor (host/guest) level. It allows kernel to
program a timer and recieve interrupt without supervisor execution
enviornment (M-mode/HS mode) intervention.

* palmer/riscv-sstc:
  RISC-V: Prefer sstc extension if available
  RISC-V: Enable sstc extension parsing from DT
  RISC-V: Add SSTC extension CSR details

RISC-V: Prefer sstc extension if available

2022-08-11T21:36:55+00:00

RISC-V ISA has sstc extension which allows updating the next clock event
via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
if sstc extension is available. Otherwise, it will fallback to SBI call
to maintain backward compatibility.

Reviewed-by: Anup Patel 
Signed-off-by: Atish Patra 
Reviewed-by: Guo Ren 
Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt

Merge tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2022-08-06T22:04:48+00:00

Pull RISC-V updates from Palmer Dabbelt:

 - Enabling the FPU is now a static_key

 - Improvements to the Svpbmt support

 - CPU topology bindings for a handful of systems

 - Support for systems with 64-bit hart IDs

 - Many settings have been enabled in the defconfig, including both
   support for the StarFive systems and many of the Docker requirements

There are also a handful of cleanups and improvements, as usual.

* tag 'riscv-for-linus-5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits)
  riscv: enable Docker requirements in defconfig
  riscv: convert the t-head pbmt errata to use the __nops macro
  riscv: introduce nops and __nops macros for NOP sequences
  RISC-V: Add fast call path of crash_kexec()
  riscv: mmap with PROT_WRITE but no PROT_READ is invalid
  riscv/efi_stub: Add 64bit boot-hartid support on RV64
  riscv: cpu: Add 64bit hartid support on RV64
  riscv: smp: Add 64bit hartid support on RV64
  riscv: spinwait: Fix hartid variable type
  riscv: cpu_ops_sbi: Add 64bit hartid support on RV64
  riscv: dts: sifive: "fix" pmic watchdog node name
  riscv: dts: canaan: Add k210 topology information
  riscv: dts: sifive: Add fu740 topology information
  riscv: dts: sifive: Add fu540 topology information
  riscv: dts: starfive: Add JH7100 CPU topology
  RISC-V: Add CONFIG_{NON,}PORTABLE
  riscv: config: enable SOC_STARFIVE in defconfig
  riscv: dts: microchip: Add mpfs' topology information
  riscv: Kconfig.socs: Add comments
  riscv: Kconfig.erratas: Add comments
  ...

Merge tag 'timers-v5.20-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

2022-07-28T10:33:34+00:00

Pull clockevent/source updates from Daniel Lezcano:

  - Add the missing DT bindings for the MTU nomadik timer (Linus
    Walleij)

  - Fix grammar typo in the ARM global timer Kconfig option (Randy
    Dunlap)

  - Add the tegra186 timer and use it on the tegra234 board (Thierry
    Reding)

  - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a
    workaround to overcome an ATF bug where the timer is not correctly
    initialized (AngeloGioacchino Del Regno)

  - Rework the suspend/resume approach to enable the feature on the
    timer even it is not an active clock and fix a compilation warning
    (Claudiu Beznea)

  - Add the Add R-Car Gen4 timer support along with the DT bindings
    (Wolfram Sang)

  - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren)

  - Fix Kconfig option to put it back to 'bool' instead of 'tristate'
    for the tegra186 (Daniel Lezcano)

  - Sort 'family,type' DT bindings for the Renesas timers (Geert
    Uytterhoeven)

  - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel
    Holland)

  - Remove unnecessary (void*) conversions for sun4i (XU pengfei)

  - Remove unnecessary (void*) conversions for sun5i (Li zeming)

Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org

clocksource/drivers/sun5i: Remove unnecessary (void*) conversions

2022-07-27T15:01:52+00:00

Remove unnecessary void* type castings.

Signed-off-by: Li zeming 
Link: https://lore.kernel.org/r/20220727083751.5540-1-zeming@nfschina.com
Signed-off-by: Daniel Lezcano

clocksource/drivers/sun4i: Remove unnecessary (void*) conversions

2022-07-27T15:01:52+00:00

Remove unnecessary void* type casting.

Signed-off-by: XU pengfei 
Link: https://lore.kernel.org/r/20220720020735.3771-1-xupengfei@nfschina.com
Signed-off-by: Daniel Lezcano

clocksource/drivers/tegra186: Put Kconfig option 'tristate' to 'bool'

2022-07-27T15:00:49+00:00

The clocksources are built-in, they are not modules. We don't know if
the core time framework is ready for clockevents / clocksources as
modules.

Revert back this option to 'bool'.

Signed-off-by: Daniel Lezcano 
Link: https://lore.kernel.org/r/20220718213657.1303538-1-daniel.lezcano@linaro.org