<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/fpga/Kconfig, branch v4.14.145</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>fpga-manager: altera-ps-spi: Fix build error</title>
<updated>2019-07-31T05:28:57+00:00</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2019-07-08T07:13:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=0d42c0dd0b3f34761582f6ddbea6f6142057d16b'/>
<id>0d42c0dd0b3f34761582f6ddbea6f6142057d16b</id>
<content type='text'>
commit 3d139703d397f6281368047ba7ad1c8bf95aa8ab upstream.

If BITREVERSE is m and FPGA_MGR_ALTERA_PS_SPI is y,
build fails:

drivers/fpga/altera-ps-spi.o: In function `altera_ps_write':
altera-ps-spi.c:(.text+0x4ec): undefined reference to `byte_rev_table'

Select BITREVERSE to fix this.

Reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Fixes: fcfe18f885f6 ("fpga-manager: altera-ps-spi: use bitrev8x4")
Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Acked-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Link: https://lore.kernel.org/r/20190708071356.50928-1-yuehaibing@huawei.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 3d139703d397f6281368047ba7ad1c8bf95aa8ab upstream.

If BITREVERSE is m and FPGA_MGR_ALTERA_PS_SPI is y,
build fails:

drivers/fpga/altera-ps-spi.o: In function `altera_ps_write':
altera-ps-spi.c:(.text+0x4ec): undefined reference to `byte_rev_table'

Select BITREVERSE to fix this.

Reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Fixes: fcfe18f885f6 ("fpga-manager: altera-ps-spi: use bitrev8x4")
Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Acked-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Link: https://lore.kernel.org/r/20190708071356.50928-1-yuehaibing@huawei.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>fpga manager: Add Altera CvP driver</title>
<updated>2017-07-17T15:26:15+00:00</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2017-06-14T15:36:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=34d1dc17ce978ae76e676d401b48fe9d004aa948'/>
<id>34d1dc17ce978ae76e676d401b48fe9d004aa948</id>
<content type='text'>
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add FPGA manager driver for loading Arria-V/Cyclone-V/Stratix-V
and Arria-10 FPGAs via CvP.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga manager: Add altera-ps-spi driver for Altera FPGAs</title>
<updated>2017-07-17T15:26:14+00:00</updated>
<author>
<name>Joshua Clayton</name>
<email>stillcompiling@gmail.com</email>
</author>
<published>2017-06-14T15:36:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=5692fae0742df7587189174b1cba364d22846c85'/>
<id>5692fae0742df7587189174b1cba364d22846c85</id>
<content type='text'>
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.

Signed-off-by: Joshua Clayton &lt;stillcompiling@gmail.com&gt;
Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.

This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.

Signed-off-by: Joshua Clayton &lt;stillcompiling@gmail.com&gt;
Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Make FPGA a menuconfig to ease disabling it all</title>
<updated>2017-07-17T15:26:14+00:00</updated>
<author>
<name>Vincent Legoll</name>
<email>vincent.legoll@gmail.com</email>
</author>
<published>2017-06-14T15:36:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=50fa0285955899c1678c5ee47fc69dc56d17b107'/>
<id>50fa0285955899c1678c5ee47fc69dc56d17b107</id>
<content type='text'>
No need to get into the submenu to disable all FPGA-related config entries

Signed-off-by: Vincent Legoll &lt;vincent.legoll@gmail.com&gt;
Acked-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
No need to get into the submenu to disable all FPGA-related config entries

Signed-off-by: Vincent Legoll &lt;vincent.legoll@gmail.com&gt;
Acked-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Signed-off-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: Add support for Xilinx LogiCORE PR Decoupler</title>
<updated>2017-04-08T15:50:36+00:00</updated>
<author>
<name>Moritz Fischer</name>
<email>mdf@kernel.org</email>
</author>
<published>2017-03-24T15:33:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=7e961c12be424c6c1e355d469cc1b82dbf3af718'/>
<id>7e961c12be424c6c1e355d469cc1b82dbf3af718</id>
<content type='text'>
This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.

Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Sören Brinkmann &lt;soren.brinkmann@xilinx.com&gt;
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.

Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Cc: Sören Brinkmann &lt;soren.brinkmann@xilinx.com&gt;
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga pr ip: Platform driver for Altera Partial Reconfiguration IP.</title>
<updated>2017-04-08T15:45:28+00:00</updated>
<author>
<name>Matthew Gerlach</name>
<email>matthew.gerlach@linux.intel.com</email>
</author>
<published>2017-03-24T00:34:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=5b73cb5b0167833347fa0ce5525cfb488b2e2290'/>
<id>5b73cb5b0167833347fa0ce5525cfb488b2e2290</id>
<content type='text'>
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds a platform bus driver for a fpga-mgr driver
that uses the Altera Partial Reconfiguration IP component.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.</title>
<updated>2017-04-08T15:45:28+00:00</updated>
<author>
<name>Matthew Gerlach</name>
<email>matthew.gerlach@linux.intel.com</email>
</author>
<published>2017-03-24T00:34:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=d201cc17a8a31cc6c4f3944988fe9e2f04b021fb'/>
<id>d201cc17a8a31cc6c4f3944988fe9e2f04b021fb</id>
<content type='text'>
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach &lt;matthew.gerlach@linux.intel.com&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga manager: Add Xilinx slave serial SPI driver</title>
<updated>2017-04-08T15:45:28+00:00</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2017-03-24T00:34:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=061c97d13f1a69c0edcab4dc6e97788e5bf3230f'/>
<id>061c97d13f1a69c0edcab4dc6e97788e5bf3230f</id>
<content type='text'>
The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The driver loads FPGA firmware over SPI, using the "slave serial"
configuration interface on Xilinx FPGAs.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Moritz Fischer &lt;mdf@kernel.org&gt;
Acked-by: Alan Tull &lt;atull@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: Add support for Lattice iCE40 FPGAs</title>
<updated>2017-03-17T06:10:48+00:00</updated>
<author>
<name>Joel Holdsworth</name>
<email>joel@airwebreathe.org.uk</email>
</author>
<published>2017-02-27T22:14:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=21f8ba2ef378d906374a26f7abc05fb92219e9c6'/>
<id>21f8ba2ef378d906374a26f7abc05fb92219e9c6</id>
<content type='text'>
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.

Signed-off-by: Joel Holdsworth &lt;joel@airwebreathe.org.uk&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Acked-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
UltraPlus devices, through slave SPI.

Signed-off-by: Joel Holdsworth &lt;joel@airwebreathe.org.uk&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Acked-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>FPGA: Add TS-7300 FPGA manager</title>
<updated>2017-03-17T06:10:48+00:00</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2017-02-27T22:14:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=4348f7e2ae250d9b986b08c8e8ea8a402790f369'/>
<id>4348f7e2ae250d9b986b08c8e8ea8a402790f369</id>
<content type='text'>
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Acked-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Acked-by: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for loading bitstreams on the Altera Cyclone II FPGA
populated on the TS-7300 board. This is done through the configuration
and data registers offered through a memory interface between the EP93xx
SoC and the FPGA via an intermediate CPLD device.

The EP93xx SoC on the TS-7300 does not have direct means of configuring
the on-board FPGA other than by using the special memory mapped
interface to the CPLD. No other entity on the system can control the
FPGA bitstream.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Acked-by: Alan Tull &lt;atull@opensource.altera.com&gt;
Acked-by: Moritz Fischer &lt;moritz.fischer@ettus.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
