Add support for the Okaya RS800480T-7X0GP to the DRM simple panel driver. The RS800480T-7X0GP is a WVGA (800x480) panel with an 18-bit parallel LCD interface. It supports pixel clocks in the range of 30-40 MHz. This panel details can be found at: http://boundarydevices.com/product/7-800x480-display/ Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the NEC NL4827HC19-05B 480x272 panel to the DRM simple panel driver. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> [treding@nvidia.com: add .bpc field for panel] Signed-off-by: Thierry Reding <treding@nvidia.com>
The AUO B080UAN01 is an 8.0" WUXGA TFT LCD panel connected using four DSI lanes. It can be supported by the simple-panel driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
According to the data sheet, the minimum horizontal blanking interval is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the minimum working horizontal blanking interval to be 60 clocks. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
The bus format both specifies the bpc and the way the individual bits get serialized into the 7 LVDS timeslots. While the is only one standard mapping for 6 bpc and so the driver could infer the bit mapping from the bpc alone, there are more options for the 8 bpc case which makes specifiying the bus format mandatory. To keep things consistent across panels and to set a precedent for new panel additions add the proper bus format. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds the bus_format field to the HSD100PXN1 panel structure. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver. The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface. It supports pixel clocks in the range of 55-75 MHz. This panel is offered for sale by Freescale as a companion part to its' i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name MCIMX-LVDS1. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com>