linux.git/drivers/irqchip, branch v6.18 Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git irqchip/riscv-intc: Add missing free() callback in riscv_intc_domain_ops 2025-11-14T15:52:34+00:00 Nick Hu nick.hu@sifive.com 2025-11-14T07:28:44+00:00 14473a1f88596fd729e892782efc267c0097dd1d The irq_domain_free_irqs() helper requires that the irq_domain_ops->free callback is implemented. Otherwise, the kernel reports the warning message "NULL pointer, cannot free irq" when irq_dispose_mapping() is invoked to release the per-HART local interrupts. Set irq_domain_ops->free to irq_domain_free_irqs_top() to cure that. Fixes: 832f15f42646 ("RISC-V: Treat IPIs as normal Linux IRQs") Signed-off-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251114-rv-intc-fix-v1-1-a3edd1c1a868@sifive.com 
The irq_domain_free_irqs() helper requires that the irq_domain_ops->free
callback is implemented. Otherwise, the kernel reports the warning message
"NULL pointer, cannot free irq" when irq_dispose_mapping() is invoked to
release the per-HART local interrupts.

Set irq_domain_ops->free to irq_domain_free_irqs_top() to cure that.

Fixes: 832f15f42646 ("RISC-V: Treat IPIs as normal Linux IRQs")
Signed-off-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251114-rv-intc-fix-v1-1-a3edd1c1a868@sifive.com
irqchip/sifive-plic: Avoid interrupt ID 0 handling during suspend/resume 2025-10-07T08:23:22+00:00 Lucas Zampieri lzampier@redhat.com 2025-09-23T14:43:19+00:00 f75e07bf5226da640fa99a0594687c780d9bace4 According to the PLIC specification[1], global interrupt sources are assigned small unsigned integer identifiers beginning at the value 1. An interrupt ID of 0 is reserved to mean "no interrupt". The current plic_irq_resume() and plic_irq_suspend() functions incorrectly start the loop from index 0, which accesses the register space for the reserved interrupt ID 0. Change the loop to start from index 1, skipping the reserved interrupt ID 0 as per the PLIC specification. This prevents potential undefined behavior when accessing the reserved register space during suspend/resume cycles. Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation") Co-developed-by: Jia Wang <wangjia@ultrarisc.com> Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Co-developed-by: Charles Mirabile <cmirabil@redhat.com> Signed-off-by: Charles Mirabile <cmirabil@redhat.com> Signed-off-by: Lucas Zampieri <lzampier@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0 
According to the PLIC specification[1], global interrupt sources are
assigned small unsigned integer identifiers beginning at the value 1.
An interrupt ID of 0 is reserved to mean "no interrupt".

The current plic_irq_resume() and plic_irq_suspend() functions incorrectly
start the loop from index 0, which accesses the register space for the
reserved interrupt ID 0.

Change the loop to start from index 1, skipping the reserved
interrupt ID 0 as per the PLIC specification.

This prevents potential undefined behavior when accessing the reserved
register space during suspend/resume cycles.

Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Co-developed-by: Jia Wang <wangjia@ultrarisc.com>
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Co-developed-by: Charles Mirabile <cmirabil@redhat.com>
Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
Signed-off-by: Lucas Zampieri <lzampier@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0
irqchip/aspeed-scu-ic: Fix an IS_ERR() vs NULL check 2025-10-07T08:23:22+00:00 Dan Carpenter dan.carpenter@linaro.org 2025-09-27T12:26:05+00:00 196754c2a04a8ba682b00ea7c818897295c98967 of_iomap() doesn't return error pointers, it returns NULL. Fix the error checking to check for NULL pointers. Fixes: 86cd4301c285 ("irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> 
of_iomap() doesn't return error pointers, it returns NULL.  Fix the error
checking to check for NULL pointers.

Fixes: 86cd4301c285 ("irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 2025-10-04T17:36:22+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-04T17:36:22+00:00 86bcf7be1e26f2d7277df90857d93ce0ebc11370 Pull more RISC-V updates from Paul Walmsley: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons * tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits) clk: COMMON_CLK_RPMI should depend on RISCV ACPI: support BGRT table on RISC-V MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers RISC-V: Enable GPIO keyboard and event device in RV64 defconfig irqchip/riscv-rpmi-sysmsi: Add ACPI support mailbox/riscv-sbi-mpxy: Add ACPI support irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() ACPI: RISC-V: Add RPMI System MSI to GSI mapping ACPI: RISC-V: Add support to update gsi range ACPI: RISC-V: Create interrupt controller list in sorted order ACPI: scan: Update honor list for RPMI System MSI ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args() ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop irqchip: Add driver for the RPMI system MSI service group dt-bindings: Add RPMI system MSI interrupt controller bindings dt-bindings: Add RPMI system MSI message proxy bindings clk: Add clock driver for the RISC-V RPMI clock service group dt-bindings: clock: Add RPMI clock service controller bindings dt-bindings: clock: Add RPMI clock service message proxy bindings mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver ... 
Pull more RISC-V updates from Paul Walmsley:

 - Support for the RISC-V-standardized RPMI interface.

   RPMI is a platform management communication mechanism between OSes
   running on application processors, and a remote platform management
   processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip,
   mailbox, and clk changes.

 - Support for the RISC-V-standardized MPXY SBI extension.

   MPXY is a RISC-V-specific standard implementing a shared memory
   mailbox between S-mode operating systems (e.g., Linux) and M-mode
   firmware (e.g., OpenSBI). It is part of this PR since one of its use
   cases is to enable M-mode firmware to act as a single RPMI client for
   all RPMI activity on a core (including S-mode RPMI activity).
   Includes a mailbox driver.

 - Some ACPI-related updates to enable the use of RPMI and MPXY.

 - The addition of Linux-wide memcpy_{from,to}_le32() static inline
   functions, for RPMI use.

 - An ACPI Kconfig change to enable boot logos on any ACPI-using
   architecture (including RISC-V)

 - A RISC-V defconfig change to add GPIO keyboard and event device
   support, for front panel shutdown or reboot buttons

* tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits)
  clk: COMMON_CLK_RPMI should depend on RISCV
  ACPI: support BGRT table on RISC-V
  MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers
  RISC-V: Enable GPIO keyboard and event device in RV64 defconfig
  irqchip/riscv-rpmi-sysmsi: Add ACPI support
  mailbox/riscv-sbi-mpxy: Add ACPI support
  irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode()
  ACPI: RISC-V: Add RPMI System MSI to GSI mapping
  ACPI: RISC-V: Add support to update gsi range
  ACPI: RISC-V: Create interrupt controller list in sorted order
  ACPI: scan: Update honor list for RPMI System MSI
  ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args()
  ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop
  irqchip: Add driver for the RPMI system MSI service group
  dt-bindings: Add RPMI system MSI interrupt controller bindings
  dt-bindings: Add RPMI system MSI message proxy bindings
  clk: Add clock driver for the RISC-V RPMI clock service group
  dt-bindings: clock: Add RPMI clock service controller bindings
  dt-bindings: clock: Add RPMI clock service message proxy bindings
  mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
  ...
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 2025-10-04T15:52:16+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-04T15:52:16+00:00 f3826aa9962b4572d01083c84ac0f8345f121168 Pull kvm updates from Paolo Bonzini: "This excludes the bulk of the x86 changes, which I will send separately. They have two not complex but relatively unusual conflicts so I will wait for other dust to settle. guest_memfd: - Add support for host userspace mapping of guest_memfd-backed memory for VM types that do NOT use support KVM_MEMORY_ATTRIBUTE_PRIVATE (which isn't precisely the same thing as CoCo VMs, since x86's SEV-MEM and SEV-ES have no way to detect private vs. shared). This lays the groundwork for removal of guest memory from the kernel direct map, as well as for limited mmap() for guest_memfd-backed memory. For more information see: - commit a6ad54137af9 ("Merge branch 'guest-memfd-mmap' into HEAD") - guest_memfd in Firecracker: https://github.com/firecracker-microvm/firecracker/tree/feature/secret-hiding - direct map removal: https://lore.kernel.org/all/20250221160728.1584559-1-roypat@amazon.co.uk/ - mmap support: https://lore.kernel.org/all/20250328153133.3504118-1-tabba@google.com/ ARM: - Add support for FF-A 1.2 as the secure memory conduit for pKVM, allowing more registers to be used as part of the message payload. - Change the way pKVM allocates its VM handles, making sure that the privileged hypervisor is never tricked into using uninitialised data. - Speed up MMIO range registration by avoiding unnecessary RCU synchronisation, which results in VMs starting much quicker. - Add the dump of the instruction stream when panic-ing in the EL2 payload, just like the rest of the kernel has always done. This will hopefully help debugging non-VHE setups. - Add 52bit PA support to the stage-1 page-table walker, and make use of it to populate the fault level reported to the guest on failing to translate a stage-1 walk. - Add NV support to the GICv3-on-GICv5 emulation code, ensuring feature parity for guests, irrespective of the host platform. - Fix some really ugly architecture problems when dealing with debug in a nested VM. This has some bad performance impacts, but is at least correct. - Add enough infrastructure to be able to disable EL2 features and give effective values to the EL2 control registers. This then allows a bunch of features to be turned off, which helps cross-host migration. - Large rework of the selftest infrastructure to allow most tests to transparently run at EL2. This is the first step towards enabling NV testing. - Various fixes and improvements all over the map, including one BE fix, just in time for the removal of the feature. LoongArch: - Detect page table walk feature on new hardware - Add sign extension with kernel MMIO/IOCSR emulation - Improve in-kernel IPI emulation - Improve in-kernel PCH-PIC emulation - Move kvm_iocsr tracepoint out of generic code RISC-V: - Added SBI FWFT extension for Guest/VM with misaligned delegation and pointer masking PMLEN features - Added ONE_REG interface for SBI FWFT extension - Added Zicbop and bfloat16 extensions for Guest/VM - Enabled more common KVM selftests for RISC-V - Added SBI v3.0 PMU enhancements in KVM and perf driver s390: - Improve interrupt cpu for wakeup, in particular the heuristic to decide which vCPU to deliver a floating interrupt to. - Clear the PTE when discarding a swapped page because of CMMA; this bug was introduced in 6.16 when refactoring gmap code. x86 selftests: - Add #DE coverage in the fastops test (the only exception that's guest- triggerable in fastop-emulated instructions). - Fix PMU selftests errors encountered on Granite Rapids (GNR), Sierra Forest (SRF) and Clearwater Forest (CWF). - Minor cleanups and improvements x86 (guest side): - For the legacy PCI hole (memory between TOLUD and 4GiB) to UC when overriding guest MTRR for TDX/SNP to fix an issue where ACPI auto-mapping could map devices as WB and prevent the device drivers from mapping their devices with UC/UC-. - Make kvm_async_pf_task_wake() a local static helper and remove its export. - Use native qspinlocks when running in a VM with dedicated vCPU=>pCPU bindings even when PV_UNHALT is unsupported. Generic: - Remove a redundant __GFP_NOWARN from kvm_setup_async_pf() as __GFP_NOWARN is now included in GFP_NOWAIT. * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (178 commits) KVM: s390: Fix to clear PTE when discarding a swapped page KVM: arm64: selftests: Cover ID_AA64ISAR3_EL1 in set_id_regs KVM: arm64: selftests: Remove a duplicate register listing in set_id_regs KVM: arm64: selftests: Cope with arch silliness in EL2 selftest KVM: arm64: selftests: Add basic test for running in VHE EL2 KVM: arm64: selftests: Enable EL2 by default KVM: arm64: selftests: Initialize HCR_EL2 KVM: arm64: selftests: Use the vCPU attr for setting nr of PMU counters KVM: arm64: selftests: Use hyp timer IRQs when test runs at EL2 KVM: arm64: selftests: Select SMCCC conduit based on current EL KVM: arm64: selftests: Provide helper for getting default vCPU target KVM: arm64: selftests: Alias EL1 registers to EL2 counterparts KVM: arm64: selftests: Create a VGICv3 for 'default' VMs KVM: arm64: selftests: Add unsanitised helpers for VGICv3 creation KVM: arm64: selftests: Add helper to check for VGICv3 support KVM: arm64: selftests: Initialize VGICv3 only once KVM: arm64: selftests: Provide kvm_arch_vm_post_create() in library code KVM: selftests: Add ex_str() to print human friendly name of exception vectors selftests/kvm: remove stale TODO in xapic_state_test KVM: selftests: Handle Intel Atom errata that leads to PMU event overcount ... 
Pull kvm updates from Paolo Bonzini:
 "This excludes the bulk of the x86 changes, which I will send
  separately. They have two not complex but relatively unusual conflicts
  so I will wait for other dust to settle.

  guest_memfd:

   - Add support for host userspace mapping of guest_memfd-backed memory
     for VM types that do NOT use support KVM_MEMORY_ATTRIBUTE_PRIVATE
     (which isn't precisely the same thing as CoCo VMs, since x86's
     SEV-MEM and SEV-ES have no way to detect private vs. shared).

     This lays the groundwork for removal of guest memory from the
     kernel direct map, as well as for limited mmap() for
     guest_memfd-backed memory.

     For more information see:
       - commit a6ad54137af9 ("Merge branch 'guest-memfd-mmap' into HEAD")
       - guest_memfd in Firecracker:
           https://github.com/firecracker-microvm/firecracker/tree/feature/secret-hiding
       - direct map removal:
           https://lore.kernel.org/all/20250221160728.1584559-1-roypat@amazon.co.uk/
       - mmap support:
           https://lore.kernel.org/all/20250328153133.3504118-1-tabba@google.com/

  ARM:

   - Add support for FF-A 1.2 as the secure memory conduit for pKVM,
     allowing more registers to be used as part of the message payload.

   - Change the way pKVM allocates its VM handles, making sure that the
     privileged hypervisor is never tricked into using uninitialised
     data.

   - Speed up MMIO range registration by avoiding unnecessary RCU
     synchronisation, which results in VMs starting much quicker.

   - Add the dump of the instruction stream when panic-ing in the EL2
     payload, just like the rest of the kernel has always done. This
     will hopefully help debugging non-VHE setups.

   - Add 52bit PA support to the stage-1 page-table walker, and make use
     of it to populate the fault level reported to the guest on failing
     to translate a stage-1 walk.

   - Add NV support to the GICv3-on-GICv5 emulation code, ensuring
     feature parity for guests, irrespective of the host platform.

   - Fix some really ugly architecture problems when dealing with debug
     in a nested VM. This has some bad performance impacts, but is at
     least correct.

   - Add enough infrastructure to be able to disable EL2 features and
     give effective values to the EL2 control registers. This then
     allows a bunch of features to be turned off, which helps cross-host
     migration.

   - Large rework of the selftest infrastructure to allow most tests to
     transparently run at EL2. This is the first step towards enabling
     NV testing.

   - Various fixes and improvements all over the map, including one BE
     fix, just in time for the removal of the feature.

  LoongArch:

   - Detect page table walk feature on new hardware

   - Add sign extension with kernel MMIO/IOCSR emulation

   - Improve in-kernel IPI emulation

   - Improve in-kernel PCH-PIC emulation

   - Move kvm_iocsr tracepoint out of generic code

  RISC-V:

   - Added SBI FWFT extension for Guest/VM with misaligned delegation
     and pointer masking PMLEN features

   - Added ONE_REG interface for SBI FWFT extension

   - Added Zicbop and bfloat16 extensions for Guest/VM

   - Enabled more common KVM selftests for RISC-V

   - Added SBI v3.0 PMU enhancements in KVM and perf driver

  s390:

   - Improve interrupt cpu for wakeup, in particular the heuristic to
     decide which vCPU to deliver a floating interrupt to.

   - Clear the PTE when discarding a swapped page because of CMMA; this
     bug was introduced in 6.16 when refactoring gmap code.

  x86 selftests:

   - Add #DE coverage in the fastops test (the only exception that's
     guest- triggerable in fastop-emulated instructions).

   - Fix PMU selftests errors encountered on Granite Rapids (GNR),
     Sierra Forest (SRF) and Clearwater Forest (CWF).

   - Minor cleanups and improvements

  x86 (guest side):

   - For the legacy PCI hole (memory between TOLUD and 4GiB) to UC when
     overriding guest MTRR for TDX/SNP to fix an issue where ACPI
     auto-mapping could map devices as WB and prevent the device drivers
     from mapping their devices with UC/UC-.

   - Make kvm_async_pf_task_wake() a local static helper and remove its
     export.

   - Use native qspinlocks when running in a VM with dedicated
     vCPU=>pCPU bindings even when PV_UNHALT is unsupported.

  Generic:

   - Remove a redundant __GFP_NOWARN from kvm_setup_async_pf() as
     __GFP_NOWARN is now included in GFP_NOWAIT.

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (178 commits)
  KVM: s390: Fix to clear PTE when discarding a swapped page
  KVM: arm64: selftests: Cover ID_AA64ISAR3_EL1 in set_id_regs
  KVM: arm64: selftests: Remove a duplicate register listing in set_id_regs
  KVM: arm64: selftests: Cope with arch silliness in EL2 selftest
  KVM: arm64: selftests: Add basic test for running in VHE EL2
  KVM: arm64: selftests: Enable EL2 by default
  KVM: arm64: selftests: Initialize HCR_EL2
  KVM: arm64: selftests: Use the vCPU attr for setting nr of PMU counters
  KVM: arm64: selftests: Use hyp timer IRQs when test runs at EL2
  KVM: arm64: selftests: Select SMCCC conduit based on current EL
  KVM: arm64: selftests: Provide helper for getting default vCPU target
  KVM: arm64: selftests: Alias EL1 registers to EL2 counterparts
  KVM: arm64: selftests: Create a VGICv3 for 'default' VMs
  KVM: arm64: selftests: Add unsanitised helpers for VGICv3 creation
  KVM: arm64: selftests: Add helper to check for VGICv3 support
  KVM: arm64: selftests: Initialize VGICv3 only once
  KVM: arm64: selftests: Provide kvm_arch_vm_post_create() in library code
  KVM: selftests: Add ex_str() to print human friendly name of exception vectors
  selftests/kvm: remove stale TODO in xapic_state_test
  KVM: selftests: Handle Intel Atom errata that leads to PMU event overcount
  ...
Merge tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2025-10-01T23:58:24+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-01T23:58:24+00:00 9792d660a4e91d31a6b1af105ae3f1c29107e94b Pull devicetree updates from Rob Herring: "DT core: - Update dtc to upstream version v1.7.2-35-g52f07dcca47c - Add stub for of_get_next_child_with_prefix() - Convert of_msi_map_id() callers to of_msi_xlate() DT bindings: - Convert multiple text board bindings to DT schema format - Add bindings for synaptics,synaptics_i2c touchscreen controller, innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP vf610 reboot controller - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and fsl,soc-operating-points properties for CPU nodes. - Add QCom Glymur PDC and tegra264-agic interrupt controllers - Add samsung,exynos8890-mali GPU to Arm Mali Midgard - Drop Samsung S3C2410 display related bindings - Allow separate DP lane and AUX connections in dp-connector - Add some missing, undocumented vendor prefixes - Add missing '#address-cells' properties in interrupt controller bindings which dtc now warns about - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt, fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text bindings which are already covered by existing schemas. - Various binding fixes for Mediatek platforms in mailbox, regulator, pinctrl, timer, and display - Drop work-around for yamllint quoting of values containing ',' - Various spelling, typo, grammar, and duplicated words fixes in DT bindings and docs - Add binding guidelines for defining properties at top level of schemas, lack of node name ABI, and usage of simple-mfd" * tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits) dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt dt-bindings: gpu: Convert nvidia,gk20a to DT schema dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema dt-bindings: vendor-prefixes: update regex for properties without a prefix dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml scripts: dt_to_config: fix grammar and a typo in --help text dt-bindings: fix spelling, typos, grammar, duplicated words docs: dt: fix grammar and spelling of: base: Add of_get_next_child_with_prefix() stub dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c dt-bindings: soc: mediatek: pwrap: Add power-domains property dt-bindings: pinctrl: mt65xx: Allow gpio-line-names dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema dt-bindings: arm: mediatek: Support mt8183-audiosys variant dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional dt-bindings: regulator: mediatek,mt6331: Add missing compatible dt-bindings: regulator: mediatek,mt6331: Fix various regulator names dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2 ... 
Pull devicetree updates from Rob Herring:
 "DT core:

   - Update dtc to upstream version v1.7.2-35-g52f07dcca47c

   - Add stub for of_get_next_child_with_prefix()

   - Convert of_msi_map_id() callers to of_msi_xlate()

 DT bindings:

   - Convert multiple text board bindings to DT schema format

   - Add bindings for synaptics,synaptics_i2c touchscreen controller,
     innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
     vf610 reboot controller

   - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
     CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
     fsl,soc-operating-points properties for CPU nodes.

   - Add QCom Glymur PDC and tegra264-agic interrupt controllers

   - Add samsung,exynos8890-mali GPU to Arm Mali Midgard

   - Drop Samsung S3C2410 display related bindings

   - Allow separate DP lane and AUX connections in dp-connector

   - Add some missing, undocumented vendor prefixes

   - Add missing '#address-cells' properties in interrupt controller
     bindings which dtc now warns about

   - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
     fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
     bindings which are already covered by existing schemas.

   - Various binding fixes for Mediatek platforms in mailbox, regulator,
     pinctrl, timer, and display

   - Drop work-around for yamllint quoting of values containing ','

   - Various spelling, typo, grammar, and duplicated words fixes in DT
     bindings and docs

   - Add binding guidelines for defining properties at top level of
     schemas, lack of node name ABI, and usage of simple-mfd"

* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
  dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
  dt-bindings: gpu: Convert nvidia,gk20a to DT schema
  dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
  dt-bindings: vendor-prefixes: update regex for properties without a prefix
  dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
  scripts: dt_to_config: fix grammar and a typo in --help text
  dt-bindings: fix spelling, typos, grammar, duplicated words
  docs: dt: fix grammar and spelling
  of: base: Add of_get_next_child_with_prefix() stub
  dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
  dt-bindings: soc: mediatek: pwrap: Add power-domains property
  dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
  dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
  dt-bindings: arm: mediatek: Support mt8183-audiosys variant
  dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
  dt-bindings: regulator: mediatek,mt6331: Add missing compatible
  dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
  dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
  ...
Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2025-09-30T23:00:29+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-09-30T23:00:29+00:00 03a53e09cd723295ac1ddd16d9908d1680e7a1bf Pull irq chip driver updates from Thomas Gleixner: - Use the startup/shutdown callbacks for the PCI/MSI per device interrupt domains. This allows us to initialize the RISCV PLIC interrupt hierarchy correctly and provides a mechanism to decouple the masking and unmasking during run-time from the expensive PCI mask and unmask when the underlying MSI provider implementation allows the interrupt to be masked. - Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that the affinity assignment works correctly by switching it over to the startup/shutdown scheme - Allow MSI providers to opt out from masking a PCI/MSI interrupt at the PCI device during operation when the provider can mask the interrupt at the underlying interrupt chip. This reduces the overhead in scenarios where disable_irq()/enable_irq() is utilized frequently by a driver. The PCI/MSI device level [un]masking is only required on startup and shutdown in this case. - Remove the conditional mask/unmask logic in the PCI/MSI layer as this is now handled unconditionally. - Replace the hardcoded interrupt routing in the Loongson EIOINTC interrupt driver to respect the firmware settings and spread them out to different CPU interrupt inputs so that the demultiplexing handler only needs to read only a single 64-bit status register instead of four, which significantly reduces the overhead in VMs as the status register access causes a VM exit. - Add support for the new AST2700 SCU interrupt controllers - Use the legacy interrupt domain setup for the Loongson PCH-LPC interrupt controller, which resembles the x86 legacy PIC setup and has the same hardcoded legacy requirements. - The usual set of cleanups, fixes and improvements all over the place * tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller PCI/MSI: Remove the conditional parent [un]mask logic irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc() irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path irqchip/gic-v5: Delete a stray tab irqchip/sg2042-msi: Set irq type according to DT configuration riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM irqchip: Use int type to store negative error codes irqchip/gic-v5: Remove the redundant ITS cache invalidation PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent() irqchip/loongson-eiointc: Add multiple interrupt pin routing support irqchip/loongson-eiointc: Route interrupt parsed from bios table ... 
Pull irq chip driver updates from Thomas Gleixner:

 - Use the startup/shutdown callbacks for the PCI/MSI per device
   interrupt domains.

   This allows us to initialize the RISCV PLIC interrupt hierarchy
   correctly and provides a mechanism to decouple the masking and
   unmasking during run-time from the expensive PCI mask and unmask when
   the underlying MSI provider implementation allows the interrupt to be
   masked.

 - Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that
   the affinity assignment works correctly by switching it over to the
   startup/shutdown scheme

 - Allow MSI providers to opt out from masking a PCI/MSI interrupt at
   the PCI device during operation when the provider can mask the
   interrupt at the underlying interrupt chip. This reduces the overhead
   in scenarios where disable_irq()/enable_irq() is utilized frequently
   by a driver.

   The PCI/MSI device level [un]masking is only required on startup and
   shutdown in this case.

 - Remove the conditional mask/unmask logic in the PCI/MSI layer as this
   is now handled unconditionally.

 - Replace the hardcoded interrupt routing in the Loongson EIOINTC
   interrupt driver to respect the firmware settings and spread them out
   to different CPU interrupt inputs so that the demultiplexing handler
   only needs to read only a single 64-bit status register instead of
   four, which significantly reduces the overhead in VMs as the status
   register access causes a VM exit.

 - Add support for the new AST2700 SCU interrupt controllers

 - Use the legacy interrupt domain setup for the Loongson PCH-LPC
   interrupt controller, which resembles the x86 legacy PIC setup and
   has the same hardcoded legacy requirements.

 - The usual set of cleanups, fixes and improvements all over the place

* tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller
  PCI/MSI: Remove the conditional parent [un]mask logic
  irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag
  irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers
  dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles
  dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
  irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization
  irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc()
  irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path
  irqchip/gic-v5: Delete a stray tab
  irqchip/sg2042-msi: Set irq type according to DT configuration
  riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
  riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
  irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment
  irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM
  irqchip: Use int type to store negative error codes
  irqchip/gic-v5: Remove the redundant ITS cache invalidation
  PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent()
  irqchip/loongson-eiointc: Add multiple interrupt pin routing support
  irqchip/loongson-eiointc: Route interrupt parsed from bios table
  ...
irqchip/riscv-rpmi-sysmsi: Add ACPI support 2025-09-26T01:49:19+00:00 Sunil V L sunilvl@ventanamicro.com 2025-08-18T04:09:18+00:00 4752b0cfbc37a4e62e583bd8723b1fc2fe8df319 Add ACPI support for the RISC-V RPMI system MSI based irqchip driver. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Link: https://lore.kernel.org/r/20250818040920.272664-23-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> 
Add ACPI support for the RISC-V RPMI system MSI based irqchip driver.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-23-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
 irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() 2025-09-26T01:49:15+00:00 Sunil V L sunilvl@ventanamicro.com 2025-08-18T04:09:16+00:00 3f5d7a5c05b4d5ac011223359f15fb140125894b ACPI based loadable drivers which need MSIs will also need imsic_acpi_get_fwnode() to update the device MSI domain so export this function. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-21-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> 
ACPI based loadable drivers which need MSIs will also need
imsic_acpi_get_fwnode() to update the device MSI domain so
export this function.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-21-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
 irqchip: Add driver for the RPMI system MSI service group 2025-09-25T20:31:56+00:00 Anup Patel apatel@ventanamicro.com 2025-08-18T04:09:09+00:00 aa43953e862c031ff66e44353c88beb7a449e80d The RPMI specification defines a system MSI service group which allows application processors to receive MSIs upon system events such as graceful shutdown/reboot request, CPU hotplug event, memory hotplug event, etc. Add an irqchip driver for the RISC-V RPMI system MSI service group to directly receive system MSIs in Linux kernel. Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> 
The RPMI specification defines a system MSI service group which
allows application processors to receive MSIs upon system events
such as graceful shutdown/reboot request, CPU hotplug event, memory
hotplug event, etc.

Add an irqchip driver for the RISC-V RPMI system MSI service group
to directly receive system MSIs in Linux kernel.

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-14-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>