linux.git/drivers/memory, branch v5.1.18

memory: tegra: Fix integer overflow on tick value calculation

2019-05-25T16:16:38+00:00

commit b906c056b6023c390f18347169071193fda57dde upstream.

Multiplying the Memory Controller clock rate by the tick count results
in an integer overflow and in result the truncated tick value is being
programmed into hardware, such that the GR3D memory client performance is
reduced by two times.

Cc: stable 
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding 
Signed-off-by: Greg Kroah-Hartman

memory: tegra: Clean up error messages

2019-01-16T12:54:13+00:00

Make all messages to start with a lower case and don't unnecessarily go
over 80 chars in the code.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Joerg Roedel

memory: tegra: Do not ask for IRQ sharing

2019-01-16T12:54:13+00:00

Memory Controller driver never shared IRQ with any other driver and very
unlikely that it will. Hence there is no need to request IRQ sharing and
the corresponding flag can be dropped safely.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Joerg Roedel

memory: tegra: Do not try to probe SMMU on Tegra20

2019-01-16T12:54:13+00:00

Tegra20 doesn't have SMMU. Move out checking of the SMMU presence from
the SMMU driver into the Memory Controller driver. This change makes code
consistent in regards to how GART/SMMU presence checking is performed.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Joerg Roedel

iommu/tegra: gart: Integrate with Memory Controller driver

2019-01-16T12:54:12+00:00

The device-tree binding has been changed. There is no separate GART device
anymore, it is squashed into the Memory Controller. Integrate GART module
with the MC in a way it is done for the SMMU on Tegra30+.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Joerg Roedel

memory: tegra: Use relaxed versions of readl/writel

2019-01-16T12:54:12+00:00

There is no need for inserting of memory barriers to access registers of
Memory Controller. Hence use the relaxed versions of the accessors.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Use of_device_get_match_data()

2019-01-16T12:54:12+00:00

There is no need to match device with the DT node since it was already
matched, use of_device_get_match_data() helper to get the match-data.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Read client ID on GART page fault

2019-01-16T12:54:11+00:00

With the device tree binding changes, now Memory Controller has access to
GART registers. Hence it is now possible to read client ID on GART page
fault to get information about what memory client causes the fault.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Adapt to Tegra20 device-tree binding changes

2019-01-16T12:54:11+00:00

The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Don't invoke Tegra30+ specific memory timing setup on Tegra20

2019-01-16T12:54:11+00:00

This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.

Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc driver")
Signed-off-by: Dmitry Osipenko 
Acked-by: Jon Hunter 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel