linux.git/drivers/memory, branch v6.6.45

memory: fsl_ifc: Make FSL_IFC config visible and selectable

2024-08-03T06:53:27+00:00

[ Upstream commit 9ba0cae3cac07c21c583f9ff194f74043f90d29c ]

While use of fsl_ifc driver with NAND flash is fine, as the fsl_ifc_nand
driver selects FSL_IFC automatically, we need the CONFIG_FSL_IFC option to
be selectable for platforms using fsl_ifc with NOR flash.

Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers")
Reviewed-by: Miquel Raynal 
Signed-off-by: Esben Haabendal 
Link: https://lore.kernel.org/r/20240530-fsl-ifc-config-v3-1-1fd2c3d233dd@geanix.com
Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Sasha Levin

memory: tegra: Correct DLA client names

2024-03-26T22:19:32+00:00

[ Upstream commit 51d915cbeef4c7a154f5d810b1e10d8125f2b0cc ]

Some of the names for the Tegra234 DLA clients are not unique and do not
align with the name of the client ID definitions. Therefore, it is not
possible to determine the exact DLA client from messages that print the
client name. Fix this by correcting the DLA memory client names for
Tegra234 to align with the name of the corresponding memory client ID.

Note that although the client names are also used by the interconnect
framework, interconnect support for the DLA clients has not been added
and so this issue does not impact the interconnect support.

Fixes: 5cd24ca0985f ("memory: tegra: Add DLA clients for Tegra234")
Signed-off-by: Jon Hunter 
Link: https://lore.kernel.org/r/20240220124430.19072-1-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Sasha Levin

memory: tegra: Set BPMP msg flags to reset IPC channels

2023-11-20T10:59:17+00:00

[ Upstream commit f344675a34383ae26a8230f4b1cd99cbd0defebd ]

Set the 'TEGRA_BPMP_MESSAGE_RESET' bit in newly added 'flags' field
of 'struct tegra_bpmp_message' to request for the reset of BPMP IPC
channels. This is used along with the 'suspended' check in BPMP driver
for handling early bandwidth requests due to the hotplug of CPU's
during system resume before the driver gets resumed.

Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth")
Co-developed-by: Sumit Gupta 
Signed-off-by: Sumit Gupta 
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

memory: tegra: add MC client for Tegra234 GPU

2023-08-05T07:01:31+00:00

Add the Non-ISO MC client for the Tegra234 GPU to the
tegra234_mc_clients table.

Signed-off-by: Sumit Gupta 
Link: https://lore.kernel.org/r/20230801121023.27841-1-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski

memory: Explicitly include correct DT includes

2023-07-25T20:09:37+00:00

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring 
Link: https://lore.kernel.org/r/20230714174717.4059518-1-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski

memory: tegra: Prefer octal over symbolic permissions

2023-07-25T20:09:36+00:00

checkpatch recommends using octal permissions instead of symbolic
permissions. Switch the debugfs files to use the former to silence
these warnings.

Signed-off-by: Thierry Reding 
Link: https://lore.kernel.org/r/20230714150116.2823766-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski

memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported

2023-07-25T20:09:36+00:00

Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the
BPMP-FW before making the MRQ request. Currently, if the BPMP-FW
doesn't support this MRQ, then the "tegra186_emc_probe" fails.
Due to this the Memory Interconnect initialization also doesn't
happen. Memory Interconnect is not dependent on this MRQ and can
initialize even when this MRQ is not supported in any platform.
The check ensures that the MRQ is called only when it is supported
by the BPMP-FW and Interconnect initializes independent of this MRQ.
Also, moved the code to new function for better readability.

Signed-off-by: Sumit Gupta 
Acked-by: Thierry Reding 
Link: https://lore.kernel.org/r/20230621134400.23070-4-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add clients used by DRM in Tegra234

2023-07-25T20:09:36+00:00

Add entries for VIC, NVDEC, NVENC, NVJPG memory controller
clients into the 'tegra_234_mc_clients' table.

Signed-off-by: Johnny Liu 
Signed-off-by: Sumit Gupta 
Acked-by: Thierry Reding 
Link: https://lore.kernel.org/r/20230621134400.23070-3-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski

memory: tegra: sort tegra234_mc_clients table as per register offsets

2023-07-25T20:09:35+00:00

Sort the MC client entries in "tegra234_mc_clients" table as per the
override and security register offsets. This will help to avoid
creating duplicate entries.

Signed-off-by: Sumit Gupta 
Acked-by: Thierry Reding 
Link: https://lore.kernel.org/r/20230621134400.23070-2-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski

memory: tegra: make icc_set_bw return zero if BWMGR not supported

2023-07-25T20:09:20+00:00

Return zero from icc_set_bw() to MC client driver if MRQ_BWMGR_INT
is not supported by the BPMP-FW. Currently, 'EINVAL' is returned
which causes error message in client drivers even when the platform
doesn't support scaling.

Fixes: 9365bf006f53 ("PCI: tegra194: Add interconnect support in Tegra234")
Signed-off-by: Sumit Gupta 
Acked-by: Thierry Reding 
Link: https://lore.kernel.org/r/20230621134400.23070-5-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski