Add a check for skip_cmu_cfg when configuring the serdes lane.  All
individual serdeses are reset upon first configuration. Resetting the
serdes involves reconfiguring it with preset values. The serdesmode is
required to determine the clock-providing CMU, therefore make sure the
serdes is not reconfigured if the serdesmode is not set.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

CMUs should not be powered up by default anymore, so remove responsible
code.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

Power on the CMU instance, that provides the clock for the serdes, given the
specified serdes mode and index. The CMU instance is looked up, using a
preset map of serdes mode and index to CMU index.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-6-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

All CMUs are powered up initially. This uses needless power. This patch
makes sure all CMUs are powered down by default. This involves
configuring a number reference clock and power-down registers of the
CMU.

Individual CMUs are later powered up, when the serdes lanes are
configured.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-5-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

Reorder CMU functions, as some of them are now required by the serdes
functions. No functional changes.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

All the serdes lanes of the sparx5 will transition between normal mode
and quiet mode, depending on activity. Make sure that the quiet mode is
configured optimally for all lanes initially. Although not much, this
will save a small amount of power.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-3-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

Add registers required to configure serdeses and CMUs for initial power
down.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-2-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

Pull phy updates from Vinod Koul:
 "This contains bunch of new device support and one new Sunplus driver
  along with updates which include another big round of qmp phy
  conversion.

  New support:
   - Qualcomm SC8280XP eDP & DP and USB3 UNI phy (Bjorn Andersson)
   - Rockchip rk3568 inno dsidphy (Chris Morgan)
   - ocelot-serdes phy yaml binding (Colin Foster)
   - Renesas gen2-usb phy yaml binding (Geert Uytterhoeven)
   - RGMII suport in lan966x driver (Horatiu Vultur)
   - Qualcomm SM6375 usb snps-femto-v2 bindings (Konrad Dybcio)
   - Rockchip rk356x csi-dphya (Michael Riesch)
   - Qualcomm sdm670 usb2 bindings (Richard Acayan)
   - Sunplus USB2 PHY (Vincent Shih)

  Updates:
   - Mediatek hdmi, ufs, tphy and xsphy updates to use bitfield helpers
     (Chunfeng Yun)
   - Continued Qualcomm qmp phy driver split and cleanup. More patches
     are under review and expected that next cycle might see completion
     of this activity (Dmitry Baryshkov & Johan Hovold)
   - TI wiz driver support for j7200 10g (Roger Quadros)
   - Qualcomm femto phy driver support for override params to help with
     tuning (Sandeep Maheswaram)
   - SGMII support in TI wiz driver (Siddharth Vadapalli)
   - dev_err_probe simplification (Yuan Can)"

* tag 'phy-for-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (170 commits)
  phy: phy-mtk-dp: make array driving_params static const
  dt-bindings: phy: qcom,qusb2: document sdm670 compatible
  phy: qcom-qmp-pcie: fix resource mapping for SDM845 QHP PHY
  phy: rockchip-snps-pcie3: only look for rockchip,pipe-grf on rk3588
  phy: tegra: xusb: Enable usb role switch attribute
  phy: mediatek: fix build warning of FIELD_PREP()
  phy: qcom-qmp-usb: Use dev_err_probe() to simplify code
  phy: qcom-qmp-ufs: Use dev_err_probe() to simplify code
  phy: qcom-qmp-pcie-msm8996: Use dev_err_probe() to simplify code
  phy: qcom-qmp-combo: Use dev_err_probe() to simplify code
  phy: qualcomm: call clk_disable_unprepare in the error handling
  phy: intel: Use dev_err_probe() to simplify code
  phy: tegra: xusb: Use dev_err_probe() to simplify code
  phy: qcom-snps: Use dev_err_probe() to simplify code
  phy: qcom-qusb2: Use dev_err_probe() to simplify code
  phy: qcom-qmp-pcie: Use dev_err_probe() to simplify code
  phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()
  phy: mediatek: mipi: remove register access helpers
  phy: mediatek: mipi: mt8183: use common helper to access registers
  phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask
  ...

The serdes driver contains also a mux to decide which interface type to
use. Currently the driver supports GMII/SGMII/QSGMII and partially RGMII.
As it doesn't support all the other RGMII interfaces like
RGMII_TXID/RXID/ID and it could run only at 1G.
Therefore extend this for all the other speeds(10/100) and also allow
the other interfaces.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220901121455.245103-1-horatiu.vultur@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

Makes so that the serdes driver also takes QUSGMII in consideration.
It's configured exactly as QSGMII as far as the serdes driver is
concerned.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>