linux.git/drivers/phy, branch v5.12.5

phy: ingenic: Fix a typo in ingenic_usb_phy_probe()

2021-05-14T08:52:24+00:00

[ Upstream commit 446c200ee3e8f6faf189ef6f25a0f5bb294afae4 ]

Fix the return value check typo which testing the wrong variable
in ingenic_usb_phy_probe().

Fixes: 31de313dfdcf ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.")
Reported-by: Hulk Robot 
Signed-off-by: Wei Yongjun 
Acked-by: Paul Cercueil 
Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()

2021-05-14T08:52:24+00:00

[ Upstream commit b976c987511e34a2e9b23545de912a121a9eded5 ]

Fix the return value check which testing the wrong variable
in mt7621_pci_phy_probe().

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Reported-by: Hulk Robot 
Signed-off-by: Wei Yongjun 
Reviewed-by: Sergio Paracuellos 
Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: marvell: ARMADA375_USBCLUSTER_PHY should not default to y, unconditionally

2021-05-14T08:52:24+00:00

[ Upstream commit 6cb17707aad869de163d7bf42c253caf501be4e2 ]

Merely enabling CONFIG_COMPILE_TEST should not enable additional code.
To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY
to MACH_ARMADA_375, and ask the user in case of compile-testing.

Fixes: eee47538ec1f2619 ("phy: add support for USB cluster on the Armada 375 SoC")
Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.be
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: ralink: phy-mt7621-pci: fix XTAL bitmask

2021-05-14T08:52:24+00:00

[ Upstream commit 982313c38f2f3793b6435ff50997ae96a2274f5a ]

When this was rewriten to get mainlined and start to
use 'linux/bitfield.h' headers, XTAL_MASK was wrong.
It must mask three bits but only two were used. Hence
properly fix it to make things work.

Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY")
Signed-off-by: Sergio Paracuellos 
Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup

2021-05-14T08:52:24+00:00

[ Upstream commit 7e52a39f1942b771213678c56002ce90a2f126d2 ]

commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module
present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in
wiz. However during cleanup, it removed only the MUX clock provider.
Remove the DIVIDER clock provider here.

Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I 
Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create()

2021-05-14T08:52:05+00:00

commit f7eb147d306ad2efae6837e20d2944f03be42eb4 upstream.

Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke wiz_init() immediately before invoking
of_platform_device_create().

Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I 
Reviewed-by: Swapnil Jakhade 
Cc:  # v5.10
Link: https://lore.kernel.org/r/20210319124128.13308-3-kishon@ti.com
Signed-off-by: Vinod Koul 
Signed-off-by: Greg Kroah-Hartman

phy: cadence: Sierra: Fix PHY power_on sequence

2021-05-14T08:52:05+00:00

commit 5b4f5757f83be34d1428a1ffbb68d4a1966e9aae upstream.

Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.

Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I 
Cc:  # v5.4+
Reviewed-by: Philipp Zabel 
Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com
Signed-off-by: Vinod Koul 
Signed-off-by: Greg Kroah-Hartman

phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove()

2021-05-12T06:39:39+00:00

[ Upstream commit e1723d8b87b73ab363256e7ca3af3ddb75855680 ]

This driver's remove path calls cancel_delayed_work(). However, that
function does not wait until the work function finishes. This means
that the callback function may still be running after the driver's
remove function has finished, which would result in a use-after-free.

Fix by calling cancel_delayed_work_sync(), which ensures that
the work is properly cancelled, no longer running, and unable
to re-schedule itself.

Reported-by: Hulk Robot 
Signed-off-by: Yang Yingliang 
Link: https://lore.kernel.org/r/20210407092716.3270248-1-yangyingliang@huawei.com
Signed-off-by: Vinod Koul 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

Merge tag 'phy-fixes2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

2021-02-10T09:39:23+00:00

Vinod writes:

phy: second round of phy fixes for v5.11

 - rockchip: init return and vednor prefix to dt-property
 - cpcap: bool conversion fix
 - lantiq: clock enable fix
 - lgm: kconfig depends on x86
 - mediatek: add mising MODULE_DEVICE_TABLE()

* tag 'phy-fixes2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: mediatek: Add missing MODULE_DEVICE_TABLE()
  phy: phy-brcm-sata: remove unneeded semicolon
  phy: USB_LGM_PHY should depend on X86
  phy: lantiq: rcu-usb2: wait after clock enable
  phy: rockchip: emmc, add vendor prefix to dts properties
  devicetree: phy: rockchip-emmc optional add vendor prefix
  phy: cpcap-usb: remove unneeded conversion to bool
  phy: rockchip-emmc: emmc_phy_init() always return 0

Merge tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

2021-02-09T08:32:35+00:00

Vinod writes:

phy-for-5.12

 - Updates:
   - Conversion to YAML binding for:
        - mtk-xsphy
        - mtk-tphy
        - mtk-ufs
	- HDMI PHY
	- MIPI DSI PHY
	- brcmstb-usb-phy
   - Support for BCM4908 usb phy
   - Support for Qualcomm SDX55 USB and QMP phy
   - Support for Qualcomm SM8350 aka Snapdragon 888 UFS and USB phy
   - Support for Qualcomm SDM660 USB and UFS phy
   - Support for Qualcomm SC8180X USB and UFS phy
   - Support for Qualcomm IPQ6018 USB phy
   - Stm32 phy updates

* tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
  phy: cpcap-usb: Simplify bool conversion
  phy: qcom-qmp: make a const array static, makes object smaller
  phy: zynqmp: Simplify code by using dev_err_probe()
  phy: qcom-qmp: Add support for SM8350 UFS phy
  phy: qcom-qmp: Add UFS V5 registers found in SM8350
  dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
  phy: qualcomm: usb28nm: Add MDM9607 init sequence
  dt-bindings: phy: qcom,qusb2: document ipq6018 compatible
  phy: qcom-qusb2: add QUSB2 support for IPQ6018
  phy: qcom-qmp: Add SC8180X USB phy
  phy: qcom-qmp: Add SC8180X UFS phy
  dt-bindings: phy: qcom,qmp: Add SC8180X USB phy
  dt-bindings: phy: qcom,qmp: Add SC8180X UFS to the QMP binding
  dt-bindings: phy: qcom-qusb2: Document SDM660 compatible
  phy: qcom-qusb2: Add configuration for SDM660
  phy: qcom-qusb2: Allow specifying default clock scheme
  dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350 bindings
  phy: qcom-qmp: Add SM8350 USB QMP PHYs
  dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY bindings
  phy: qcom-qmp: Add support for SDX55 QMP PHY
  ...