linux.git/drivers/pinctrl, branch v5.18

Merge tag 'pinctrl-v5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2022-05-19T16:02:41+00:00

Pull pin control fixes from Linus Walleij:

 - Fix an altmode in the Ocelot driver

 - Fix the IES control pins in the Mediatek MT8365 driver

 - Sunxi (AMLogic) driver:
    - Fix the UART2 function pin assignments
    - Fix the signal name of the PA2 SPI pin

* tag 'pinctrl-v5.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pin
  pinctrl: sunxi: fix f1c100s uart2 function
  pinctrl: mediatek: mt8365: fix IES control pins
  pinctrl: ocelot: Fix for lan966x alt mode

pinctrl: sunxi: f1c100s: Fix signal name comment for PA2 SPI pin

2022-05-13T23:07:08+00:00

The manual describes function 0x6 of pin PA2 as "SPI1_CLK", so change
the comment to reflect that.

Signed-off-by: Andre Przywara 
Acked-by: Jernej Skrabec 
Link: https://lore.kernel.org/r/20220504170736.2669595-1-andre.przywara@arm.com
Signed-off-by: Linus Walleij

pinctrl: sunxi: fix f1c100s uart2 function

2022-05-13T23:06:07+00:00

Change suniv f1c100s pinctrl,PD14 multiplexing function lvds1 to uart2

When the pin PD13 and PD14 is setting up to uart2 function in dts,
there's an error occurred:
1c20800.pinctrl: unsupported function uart2 on pin PD14

Because 'uart2' is not any one multiplexing option of PD14,
and pinctrl don't know how to configure it.

So change the pin PD14 lvds1 function to uart2.

Signed-off-by: IotaHydrae 
Reviewed-by: Andre Przywara 
Link: https://lore.kernel.org/r/tencent_70C1308DDA794C81CAEF389049055BACEC09@qq.com
Signed-off-by: Linus Walleij

Merge tag 'aspeed-v5.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/fixes

2022-05-03T14:06:29+00:00

ASPEED device tree fixes for v5.18

 - Quad SPI device tree corrections

 - Reinstate GFX node that was removed

 - romed8hm3 machine fixes

* tag 'aspeed-v5.18-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
  ARM: dts: aspeed: Add video engine to g6
  ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
  ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
  ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group
  ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi
  dt-bindings: pinctrl: aspeed-g6: add FWQSPI function/group
  pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group
  dt-bindings: pinctrl: aspeed-g6: remove FWQSPID group
  pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl
  ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi

Link: https://lore.kernel.org/r/CACPK8XdhLfafOfqvR0r7p6V6AhtNXD4uZGaz7Y+Y4P-rc9p0tQ@mail.gmail.com
Signed-off-by: Arnd Bergmann

pinctrl: mediatek: mt8365: fix IES control pins

2022-05-01T21:24:18+00:00

IES26 (BIT 16 of IES1_CFG_ADDR) controls the following pads:

- PAD_I2S_DATA_IN (GPIO114)
- PAD_I2S_LRCK (GPIO115)
- PAD_I2S_BCK (GPIO116)

The pinctrl table is wrong since it lists pins 114 to 112.

Update the table with the correct values.

Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC")
Reported-by: Youngmin Han 
Signed-off-by: Mattijs Korpershoek 
Link: https://lore.kernel.org/r/20220426125714.298907-1-mkorpershoek@baylibre.com
Signed-off-by: Linus Walleij

pinctrl: ocelot: Fix for lan966x alt mode

2022-05-01T21:24:18+00:00

For lan966x, the GPIO 35 has the wrong function for alternate mode 2.
The mode is not none but is PTP sync.

Fixes: 531d6ab36571c2 ("pinctrl: ocelot: Extend support for lan966x")
Signed-off-by: Horatiu Vultur 
Reviewed-by: Kavyasree Kotagiri 
Link: https://lore.kernel.org/r/20220413192918.3777234-1-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij

pinctrl: pistachio: fix use of irq_of_parse_and_map()

2022-04-24T14:24:09+00:00

The irq_of_parse_and_map() function returns 0 on failure, and does not
return an negative value.

Fixes: cefc03e5995e ("pinctrl: Add Pistachio SoC pin control driver")
Reported-by: Zeal Robot 
Signed-off-by: Lv Ruyi 
Link: https://lore.kernel.org/r/20220424031430.3170759-1-lv.ruyi@zte.com.cn
Signed-off-by: Linus Walleij

pinctrl: stm32: Keep pinctrl block clock enabled when LEVEL IRQ requested

2022-04-22T22:10:11+00:00

The current EOI handler for LEVEL triggered interrupts calls clk_enable(),
register IO, clk_disable(). The clock manipulation requires locking which
happens with IRQs disabled in clk_enable_lock(). Instead of turning the
clock on and off all the time, enable the clock in case LEVEL interrupt is
requested and keep the clock enabled until all LEVEL interrupts are freed.
The LEVEL interrupts are an exception on this platform and seldom used, so
this does not affect the common case.

This simplifies the LEVEL interrupt handling considerably and also fixes
the following splat found when using preempt-rt:
 ------------[ cut here ]------------
 WARNING: CPU: 0 PID: 0 at kernel/locking/rtmutex.c:2040 __rt_mutex_trylock+0x37/0x62
 Modules linked in:
 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.109-rt65-stable-standard-00068-g6a5afc4b1217 #85
 Hardware name: STM32 (Device Tree Support)
 [] (unwind_backtrace) from [] (show_stack+0xb/0xc)
 [] (show_stack) from [] (dump_stack+0x6f/0x84)
 [] (dump_stack) from [] (__warn+0x7f/0xa4)
 [] (__warn) from [] (warn_slowpath_fmt+0x3b/0x74)
 [] (warn_slowpath_fmt) from [] (__rt_mutex_trylock+0x37/0x62)
 [] (__rt_mutex_trylock) from [] (rt_spin_trylock+0x7/0x16)
 [] (rt_spin_trylock) from [] (clk_enable_lock+0xb/0x80)
 [] (clk_enable_lock) from [] (clk_core_enable_lock+0x9/0x18)
 [] (clk_core_enable_lock) from [] (stm32_gpio_get+0x11/0x24)
 [] (stm32_gpio_get) from [] (stm32_gpio_irq_trigger+0x1f/0x48)
 [] (stm32_gpio_irq_trigger) from [] (handle_fasteoi_irq+0x71/0xa8)
 [] (handle_fasteoi_irq) from [] (generic_handle_irq+0x19/0x22)
 [] (generic_handle_irq) from [] (__handle_domain_irq+0x55/0x64)
 [] (__handle_domain_irq) from [] (gic_handle_irq+0x53/0x64)
 [] (gic_handle_irq) from [] (__irq_svc+0x65/0xc0)
 Exception stack(0xc0e01f18 to 0xc0e01f60)
 1f00:                                                       0000300c 00000000
 1f20: 0000300c c010ff01 00000000 00000000 c0e00000 c0e07714 00000001 c0e01f78
 1f40: c0e07758 00000000 ef7cd0ff c0e01f68 c010554b c0105542 40000033 ffffffff
 [] (__irq_svc) from [] (arch_cpu_idle+0xc/0x1e)
 [] (arch_cpu_idle) from [] (default_idle_call+0x21/0x3c)
 [] (default_idle_call) from [] (do_idle+0xe3/0x1e4)
 [] (do_idle) from [] (cpu_startup_entry+0x13/0x14)
 [] (cpu_startup_entry) from [] (start_kernel+0x397/0x3d4)
 [] (start_kernel) from [<00000000>] (0x0)
 ---[ end trace 0000000000000002 ]---

Power consumption measured on STM32MP157C DHCOM SoM is not increased or
is below noise threshold.

Fixes: 47beed513a85b ("pinctrl: stm32: Add level interrupt support to gpio irq chip")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Fabien Dessenne 
Cc: Linus Walleij 
Cc: Marc Zyngier 
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
To: linux-gpio@vger.kernel.org
Reviewed-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20220421140827.214088-1-marex@denx.de
Signed-off-by: Linus Walleij

pinctrl: rockchip: sort the rk3308_mux_recalced_data entries

2022-04-22T21:36:24+00:00

All the entries are sorted according to num/pin except for two
entries. Sort them too.

Signed-off-by: Luca Ceresoli 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20220420142432.248565-2-luca.ceresoli@bootlin.com
Signed-off-by: Linus Walleij

pinctrl: rockchip: fix RK3308 pinmux bits

2022-04-22T21:36:24+00:00

Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong,
pointing to non-existing registers.

Fix the entire table.

Also add a comment in front of each entry with the same string that appears
in the datasheet to make the table easier to compare with the docs.

This fix has been tested on real hardware for the gpio3b3_sel entry.

Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support")
Signed-off-by: Luca Ceresoli 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20220420142432.248565-1-luca.ceresoli@bootlin.com
Signed-off-by: Linus Walleij