linux.git/drivers/pwm, branch v6.1.2

pwm: tegra: Fix 32 bit build

2022-12-31T12:33:12+00:00

[ Upstream commit dd1f1da4ada5d8ac774c2ebe97230637820b3323 ]

The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
integer causing a build warning/error (and the value truncated):

  drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
  drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
    148 |   required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
        |                                                     ^~

Explicitly cast to a u64 to ensure the correct result.

Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
Signed-off-by: Steven Price 
Reviewed-by: Uwe Kleine-König 
Reviewed-by: Jon Hunter 
Signed-off-by: Sasha Levin

pwm: mediatek: always use bus clock for PWM on MT7622

2022-12-31T12:32:51+00:00

[ Upstream commit aa3c668f2f98856af96e13f44da6ca4f26f0b98c ]

According to MT7622 Reference Manual for Development Board v1.0 the PWM
unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register
at offset 0x210 just like other modern MediaTek ARM64 SoCs.
And also MT7622 sets that register to 0x00000001 on reset which is
described as 'Select 26M fix CLK as BCLK' in the datasheet.
Hence set has_ck_26m_sel to true also for MT7622 which results in the
driver writing 0 to the PWM_CK_26M_SEL register which is described as
'Select bus CLK as BCLK'.

Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock")
Signed-off-by: Daniel Golle 
Reviewed-by: AngeloGioacchino Del Regno 
Acked-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/Y1iF2slvSblf6bYK@makrotopia.org
Signed-off-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

pwm: mtk-disp: Fix the parameters calculated by the enabled flag of disp_pwm

2022-12-31T12:32:51+00:00

[ Upstream commit 0b5ef3429d8f78427558ab0dcbfd862098ba2a63 ]

In the original mtk_disp_pwm_get_state() function wrongly uses bit 0 of
CON0 to judge if the PWM is enabled.
However that is indicated by a bit (at a machine dependent position) in
the DISP_PWM_EN register. Fix this accordingly.

Fixes: 3f2b16734914 ("pwm: mtk-disp: Implement atomic API .get_state()")
Signed-off-by: xinlei lee 
Reviewed-by: Uwe Kleine-König 
Reviewed-by: AngeloGioacchino Del Regno 
Link: https://lore.kernel.org/r/1666172538-11652-1-git-send-email-xinlei.lee@mediatek.com
Signed-off-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

pwm: sifive: Call pwm_sifive_update_clock() while mutex is held

2022-12-31T12:32:51+00:00

[ Upstream commit 45558b3abb87eeb2cedb8a59cb2699c120b5102a ]

As was documented in commit 0f02f491b786 ("pwm: sifive: Reduce time the
controller lock is held") a caller of pwm_sifive_update_clock() must
hold the mutex. So fix pwm_sifive_clock_notifier() to grab the lock.

While this necessity was only documented later, the race exists since
the driver was introduced.

Fixes: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM")
Reported-by: Emil Renner Berthing 
Reviewed-by: Emil Renner Berthing 
Link: https://lore.kernel.org/r/20221018061656.1428111-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

pwm: tegra: Ensure the clock rate is not less than needed

2022-12-31T12:32:48+00:00

[ Upstream commit 5eccd0d9fabc4d2ab8d2a0c056fb1d7e2ff892fc ]

When dynamically scaling the PWM clock, the function
dev_pm_opp_set_rate() may set the PWM clock to a rate that is lower than
what is required. The clock rate requested when calling
dev_pm_opp_set_rate() is the minimum clock rate that is needed to drive
the PWM to achieve the required period. Hence, if the actual clock
rate is less than the requested clock rate, then the required period
cannot be achieved and configuring the PWM fails. Fix this by
calling clk_round_rate() to check if the clock rate that will be provided
is sufficient and if not, double the required clock rate to ensure the
required period can be attained.

Fixes: 8c193f4714df ("pwm: tegra: Optimize period calculation")
Signed-off-by: Jon Hunter 
Acked-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

pwm: tegra: Improve required rate calculation

2022-12-31T12:32:48+00:00

[ Upstream commit f271946117dde2ca8741b8138b347b2d68e6ad56 ]

For the case where dev_pm_opp_set_rate() is called to set the PWM clock
rate, the requested rate is calculated as ...

 required_clk_rate = (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;

The above calculation may lead to rounding errors because the
NSEC_PER_SEC is divided by 'period_ns' before applying the
PWM_DUTY_WIDTH multiplication factor. For example, if the period is
45334ns, the above calculation yields a rate of 5646848Hz instead of
5646976Hz. Fix this by applying the multiplication factor before
dividing and using the DIV_ROUND_UP macro which yields the expected
result of 5646976Hz.

Fixes: 1d7796bdb63a ("pwm: tegra: Support dynamic clock frequency configuration")
Signed-off-by: Jon Hunter 
Reviewed-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding 
Signed-off-by: Sasha Levin

Merge tag 'pwm/for-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

2022-10-07T18:32:10+00:00

Pull pwm updates from Thierry Reding:
 "The Rockchip and Mediatek drivers gain support for more chips and the
  LPSS driver undergoes some refactoring and receives some improvements.

  Other than that there are various cleanups of the core"

* tag 'pwm/for-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: sysfs: Replace sprintf() with sysfs_emit()
  pwm: core: Replace custom implementation of device_match_fwnode()
  pwm: lpss: Add a comment to the bypass field
  pwm: lpss: Make use of bits.h macros for all masks
  pwm: lpss: Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr() macros
  pwm: lpss: Use device_get_match_data() to get device data
  pwm: lpss: Move resource mapping to the glue drivers
  pwm: lpss: Move exported symbols to PWM_LPSS namespace
  pwm: lpss: Deduplicate board info data structures
  dt-bindings: pwm: Add compatible for Mediatek MT8188
  dt-bindings: pwm: rockchip: Add rockchip,rk3128-pwm
  dt-bindings: pwm: rockchip: Add description for rk3588
  pwm: sysfs: Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  pwm: rockchip: Convert to use dev_err_probe()

Merge tag 'hwmon-for-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging

2022-10-05T02:02:54+00:00

Pull hwmon updates from Guenter Roeck:
 "New drivers:

   - Driver for MAX31760 fan speed controller

   - Driver for TEXAS TPS546D24 Buck Converter

   - Driver for EMC2301/2/3/5 RPM-based PWM Fan Speed Controller

  Removed drivers:

   - Drop obsolete asus_wmi_ec_sensors driver

  Cleanups, affecting various drivers:

   - Use DEFINE_SIMPLE_DEV_PM_OPS where appropriate

   - Remove forward declarations

   - Move from strlcpy with unused retval to strscpy

   - Make use of devm_clk_get_enabled()

   - Drop devm_of_pwm_get()

  Other notable cleanup and improvements:

   - Support for additional USB devide ID and support for reporting of
     rail mode via debugfs added to corsair-psu driver

   - Support for aditional USB ID in nzxt-smart2 driver

   - Support for Aquacomputer High Flow Next in aquacomputer_d5next
     driver

   - Major cleanup of pwm-fan driver

   - Major cleanup of mr75203 driver, and added support for new device
     revision

  And various other minor fixes and cleanups"

* tag 'hwmon-for-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging: (86 commits)
  hwmon: (corsair-psu) add USB id of new revision of the HX1000i psu
  hwmon: (pmbus/mp2888) Fix sensors readouts for MPS Multi-phase mp2888 controller
  dt-bindings: hwmon: sensirion,shtc1: Clean up spelling mistakes and grammar
  hwmon: (nct6683) remove unused variable in nct6683_create_attr_group
  hwmon: w83627hf: Reorder symbols to get rid of a few forward declarations
  hwmon: (ina3221) Use DEFINE_RUNTIME_DEV_PM_OPS() and pm_ptr()
  hwmon: (w83627ehf) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (tmp108) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (tmp103) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (tmp102) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (pwm-fan) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (nct6775) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (max6639) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (max31730) witch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (max31722) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (ltc2947) Switch to EXPORT_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (lm90) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (it87) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (gpio-fan) Switch to DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  hwmon: (adt7x10) Switch to EXPORT_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr()
  ...

pwm: sysfs: Replace sprintf() with sysfs_emit()

2022-09-28T15:52:02+00:00

While the uses in this code are unproblematic, it's generally safer for
sysfs outputs to use the new sysfs_emit() helper instead of raw calls to
sprintf() and friends. This also has the benefit of annotating the uses,
which makes them easier to audit and potentially use them to generate
sysfs documentation from them.

This patch replaces existing sprintf() calls straightforwardly with the
new helper.

Signed-off-by: Andy Shevchenko 
Reviewed-by: Uwe Kleine-König 
Signed-off-by: Thierry Reding

pwm: core: Replace custom implementation of device_match_fwnode()

2022-09-28T14:54:25+00:00

Replace custom implementation of the device_match_fwnode(). This hides
the implementation details and makes future changes easier.

Signed-off-by: Andy Shevchenko 
Signed-off-by: Thierry Reding