[ Upstream commit 16de4c6a8fe9ff497ca1aba33ef0dbee09f11952 ]

This is a special device that's created dynamically and is supposed to
stay in memory forever. We also currently don't have a devlink between
it and the actual reset consumer. Suppress sysfs bind attributes so that
user-space can't unbind the device because - as of now - it will cause a
use-after-free splat from any user that puts the reset control handle.

Fixes: cee544a40e44 ("reset: gpio: Add GPIO-based reset controller")
Cc: stable@vger.kernel.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

[ Upstream commit c7a5e01e229d21e0560d78bd645b4f7398667ce4 ]

The driver doesn't use any symbols depending on CONFIG_OF, so drop the
dependency. Also, enable it by default when ARCH_CANAAN is selected.

Fixes: 360a7a647759 ("reset: canaan: add reset driver for Kendryte K230")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

As per the i.MX8MP TRM, section 14.2 "AUDIO_BLK_CTRL", table 14.2.3.1.1
"memory map", the definition of the EARC control register shows that the
EARC controller software reset is controlled via bit 0, while the EARC PHY
software reset is controlled via bit 1.

This means that the current definitions of IMX8MP_AUDIOMIX_EARC_RESET_MASK
and IMX8MP_AUDIOMIX_EARC_PHY_RESET_MASK are wrong since their values would
imply that the EARC controller software reset is controlled via bit 1 and
the EARC PHY software reset is controlled via bit 2. Fix them.

Fixes: a83bc87cd30a ("reset: imx8mp-audiomix: Prepare the code for more reset bits")
Cc: stable@vger.kernel.org
Reviewed-by: Shengjiu Wang <shengjiu.wang@gmail.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Pull SoC driver updates from Arnd Bergmann:
 "Lots of platform specific updates for Qualcomm SoCs, including a new
  TEE subsystem driver for the Qualcomm QTEE firmware interface.

  Added support for the Apple A11 SoC in drivers that are shared with
  the M1/M2 series, among more updates for those.

  Smaller platform specific driver updates for Renesas, ASpeed,
  Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
  SoCs.

  Driver updates in the cache controller, memory controller and reset
  controller subsystems.

  SCMI firmware updates to add more features and improve robustness.
  This includes support for having multiple SCMI providers in a single
  system.

  TEE subsystem support for protected DMA-bufs, allowing hardware to
  access memory areas that managed by the kernel but remain inaccessible
  from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  tee: fix register_shm_helper()
  pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
  dt-bindings: spmi: Add Apple A11 and T2 compatible
  serial: qcom-geni: Load UART qup Firmware from linux side
  spi: geni-qcom: Load spi qup Firmware from linux side
  i2c: qcom-geni: Load i2c qup Firmware from linux side
  soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
  soc: qcom: geni-se: Cleanup register defines and update copyright
  dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
  Documentation: tee: Add Qualcomm TEE driver
  tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
  tee: qcom: add primordial object
  tee: add Qualcomm TEE driver
  tee: increase TEE_MAX_ARG_SIZE to 4096
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
  tee: add close_context to TEE driver operation
  ...

Make sure to drop the OF node reference taken when probing the auxiliary
device when the device is later unbound.

Fixes: 487b1b32e317 ("reset: eyeq: add platform driver")
Cc: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250708085613.15823-1-johan@kernel.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

When using MMIO with regmap, fast_io is implied. No need to set it
again.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Drew Fustini <fustini@kernel.org> # for reset-th1520.c
Link: https://lore.kernel.org/r/20250813161517.4746-17-wsa+renesas@sang-engineering.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The VO subsystem of TH1520 contains a few resets for the display
pipeline -- display, MIPI DSI and HDMI controllers.

Add support for them to the reset-th1520 driver.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250813081716.2181843-3-uwu@icenowy.me
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The AST2700 reset driver is registered as an auxiliary device
due to reset and clock controller share the same register region.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250708052909.4145983-3-ryan_chen@aspeedtech.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The ephy control register on bcm63xx SoCs contain bits for
resetting individual internal phys. Use the existing bcm6345-reset
driver to set bits.

Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
Link: https://lore.kernel.org/r/20250715234605.36216-2-kylehendrydev@gmail.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Pull clk updates from Stephen Boyd:
 "This is the usual collection of primarily clk driver updates.

  The big part of the diff is all the new Qualcomm clk drivers added for
  a few SoCs they're working on. The other two vendors with significant
  work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
  to existing drivers and supports some new SoCs while Amlogic is
  starting a significant refactoring to simplify their code.

  The core framework gained a pair of helpers to get the 'struct device'
  or 'struct device_node' associated with a 'struct clk_hw'. Some
  associated KUnit tests were added for these simple helpers as well.

  Beyond that core change there are lots of little fixes throughout the
  clk drivers for the stuff we see every day, wrong clk driver data that
  affects tree topology or supported frequencies, etc. They're not found
  until the clks are actually used by some consumer device driver.

  New Drivers:
   - Global, display, gpu, video, camera, tcsr, and rpmh clock
     controller for the Qualcomm Milos SoC
   - Camera, display, GPU, and video clock controllers for Qualcomm
     QCS615
   - Video clock controller driver for Qualcomm SM6350
   - Camera clock controller driver for Qualcomm SC8180X
   - I3C clocks and resets on Renesas RZ/G3E
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/V2H(P) and RZ/V2N
   - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
   - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
   - Ethernet clocks and resets on Renesas RZ/G3E
   - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
     (R9A09G087) SoCs
   - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
   - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
     RZ/V2N

  Updates:
   - Support atomic PWMs in the PWM clk driver
   - clk_hw_get_dev() and clk_hw_get_of_node() helpers
   - Replace round_rate() with determine_rate() in various clk drivers
   - Convert clk DT bindings to DT schema format for DT validation
   - Various clk driver cleanups and refactorings from static analysis
     tools and possibly real humans
   - A lot of little fixes here and there to things like clk tree
     topology, missing frequencies, flagging clks as critical, etc"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
  clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
  ...