linux.git/drivers/soc/imx, branch v5.16.1

soc: imx: Register SoC device only on i.MX boards

2021-12-08T12:30:00+00:00

At the moment, using the ARM32 multi_v7_defconfig always results in two
SoCs being exposed in sysfs. This is wrong, as far as I'm aware the
Qualcomm DragonBoard 410c does not actually make use of a i.MX SoC. :)

  qcom-db410c:/sys/devices/soc0$ grep . *
  family:Freescale i.MX
  machine:Qualcomm Technologies, Inc. APQ 8016 SBC
  revision:0.0
  serial_number:0000000000000000
  soc_id:Unknown

  qcom-db410c:/sys/devices/soc1$ grep . *
  family:Snapdragon
  machine:APQ8016
  ...

This happens because imx_soc_device_init() registers the soc device
unconditionally, even when running on devices that do not make use of i.MX.
Arnd already reported this more than a year ago and even suggested a fix
similar to this commit, but for some reason it was never submitted.

Fix it by checking if the "__mxc_cpu_type" variable was actually
initialized by earlier platform code. On devices without i.MX it will
simply stay 0.

Cc: Peng Fan 
Fixes: d2199b34871b ("ARM: imx: use device_initcall for imx_soc_device_init")
Reported-by: Arnd Bergmann 
Link: https://lore.kernel.org/r/CAK8P3a0hxO1TmK6oOMQ70AHSWJnP_CAq57YMOutrxkSYNjFeuw@mail.gmail.com/
Signed-off-by: Stephan Gerhold 
Reviewed-by: Fabio Estevam 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi reset

2021-12-06T02:28:30+00:00

Most of the blk-ctrl reset bits are found in one register, however
there are two bits in offset 8 for pulling the MIPI DPHY out of reset
and one of them needs to be set when IMX8MM_DISPBLK_PD_MIPI_CSI is brought
out of reset or the MIPI_CSI hangs.

Since MIPI_DSI is impacted, add the additional one for MIPI_DSI too.

Fixes: 926e57c065df ("soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl")
Signed-off-by: Adam Ford 
Reviewed-by: Fabio Estevam 
Reviewed-by: Lucas Stach 
Reviewed-by: Laurent Pinchart 
Tested by: Tim Harvey 
Signed-off-by: Shawn Guo

soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate()

2021-10-15T03:10:05+00:00

The > comparison should be >= to prevent reading one element beyond the
end of the array.  The onecell_data->domains[] array is allocated in
imx8m_blk_ctrl_probe() and it has "onecell_data->num_domains" elements.

Fixes: 5b340e7813d4 ("soc: imx: add i.MX8M blk-ctrl driver")
Signed-off-by: Dan Carpenter 
Reviewed-by: Lucas Stach 
Signed-off-by: Shawn Guo

soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl

2021-10-06T12:13:51+00:00

This adds the description for the i.MX8MM disp blk-ctrl.

Signed-off-by: Lucas Stach 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: add i.MX8M blk-ctrl driver

2021-10-06T12:13:47+00:00

This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of
SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX
power domains and interacts with the GPC power controller to provide the
peripherals in the power domain access to the NoC and ensures that those
peripherals are properly reset when their respective power domain is
brought back to life.

Software needs to do different things to make the bus handshake happen
after the GPC *MIX domain is powered up and before it is powered down.
As the requirements are quite different between the various blk-ctrls
there is a callback function provided to hook in the proper sequence.

The peripheral domains are quite uniform, they handle the soft clock
enables and resets in the blk-ctrl address space and sequencing with the
upstream GPC power domains.

Signed-off-by: Lucas Stach 
Acked-by: Frieder Schrempf 
Reviewed-by: Philipp Zabel 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: support system suspend/resume

2021-10-06T12:13:45+00:00

Our usage of runtime PM to control the hierarchy of power domains is
slightly unusual and means that powering up a domain may fail in early
system resume, as runtime PM is still disallowed at this stage.

However the system suspend/resume path takes care of powering down/up
the power domains in the order defined by the device parent/child and
power-domain provider/consumer hierarachy. So we can just runtime
resume all our power-domain devices to allow the power-up to work
properly in the resume path. System suspend will still disable all
domains as intended.

Signed-off-by: Lucas Stach 
Acked-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: keep i.MX8M* bus clocks enabled

2021-10-06T12:13:42+00:00

Annotate the domains with bus clocks to keep those clocks enabled
as long as the domain is active.

Signed-off-by: Lucas Stach 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: add domain option to keep domain clocks enabled

2021-10-06T12:13:39+00:00

Some of the MIX domains are using clocks to drive the bus bridges. Those
must be enabled at all times, as long as the domain is powered up and
they don't have any other consumer than the power domain. Add an option
to keep the clocks attached to a domain enabled as long as the domain
is power up and only disable them after the domain is powered down.

Signed-off-by: Lucas Stach 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: add lockdep annotation

2021-10-06T12:13:23+00:00

Some of the GPCv2 power domains are nested inside each other without
visibility to lockdep at the genpd level, as they are in separate
driver instances and don't have a parent/child power-domain relationship.

Add a subclass annotation to the nested domains to let lockdep know that
it is okay to take the genpd lock in a nested fashion.

Signed-off-by: Lucas Stach 
Reviewed-by: Peng Fan 
Signed-off-by: Shawn Guo

Revert "soc: imx: gpcv2: move reset assert after requesting domain power up"

2021-10-05T06:29:19+00:00

This reverts commit a77ebdd9f553. It turns out that the VPU domain has no
different requirements, even though the downstream ATF implementation seems
to suggest otherwise. Powering on the domain with the reset asserted works
fine. As the changed sequence has caused sporadic issues with the GPU
domains, just revert the change to go back to the working sequence.

Cc:  # 5.14
Signed-off-by: Lucas Stach 
Acked-by: Peng Fan 
Tested-by: Adam Ford  #imx8mm-beacon
Signed-off-by: Shawn Guo