linux.git/drivers/usb/dwc3, branch v5.3.2

Revert "usb:gadget Separated decoding functions from dwc3 driver."

2019-07-04T11:02:09+00:00

This reverts commit 3db1b636c07e15ff7410db782832dc2e7ffd2bce.

It's broken.

Reported-by: Stephen Rothwell 
Cc: Felipe Balbi 
Cc: Pawel Laszczak 
Signed-off-by: Greg Kroah-Hartman

usb:gadget Separated decoding functions from dwc3 driver.

2019-07-03T07:45:58+00:00

Patch moves some decoding functions from driver/usb/dwc3/debug.h driver
to driver/usb/gadget/debug.c file. These moved functions include:
    dwc3_decode_get_status
    dwc3_decode_set_clear_feature
    dwc3_decode_set_address
    dwc3_decode_get_set_descriptor
    dwc3_decode_get_configuration
    dwc3_decode_set_configuration
    dwc3_decode_get_intf
    dwc3_decode_set_intf
    dwc3_decode_synch_frame
    dwc3_decode_set_sel
    dwc3_decode_set_isoch_delay
    dwc3_decode_ctrl

These functions are used also in inroduced cdns3 driver.

All functions prefixes were changed from dwc3 to usb.
Also, function's parameters has been extended according to the name
of fields in standard SETUP packet.
Additionally, patch adds usb_decode_ctrl function to
include/linux/usb/gadget.h file.

Signed-off-by: Pawel Laszczak 
Signed-off-by: Felipe Balbi

usb: dwc3: pci: add support for TigerLake Devices

2019-07-03T07:45:11+00:00

This patch adds the necessary PCI ID for TGP-LP devices.

Signed-off-by: Felipe Balbi

usb: dwc3: remove unused @lock member of dwc3_ep struct

2019-06-20T08:50:19+00:00

The member @lock of dwc3_ep struct is only initialized,
and not used elsewhere, so remove it.

Signed-off-by: Chunfeng Yun 
Signed-off-by: Felipe Balbi

usb: dwc3: pci: Add Support for Intel Elkhart Lake Devices

2019-06-20T07:35:41+00:00

This patch simply adds a new PCI Device ID

Signed-off-by: Felipe Balbi

usb: dwc3: gadget: Add support for disabling U1 and U2 entries

2019-06-18T08:58:30+00:00

Gadget applications may have a requirement to disable the U1 and U2
entry based on the usecase. Below are few usecases where the disabling
U1/U2 entries may be possible.

Usecase 1:
When combining dwc3 with an redriver for a USB Type-C device solution, it
sometimes have problems with leaving U1/U2 for certain hosts, resulting in
link training errors and reconnects. For this U1/U2 state entries may be
avoided.

Usecase 2:
When performing performance benchmarking on mass storage gadget the
U1 and U2 entries can be disabled.

Usecase 3:
When periodic transfers like ISOC transfers are used with bInterval
of 1 which doesn't require the link to enter into U1 or U2 state entry
(since ping is issued from host for every uframe interval). In this
case the U1 and U2 entry can be disabled.

Disablement of U1/U2 can be done by setting U1DevExitLat and U2DevExitLat
values to 0 in the BOS descriptor. Host on seeing 0 value for U1DevExitLat
and U2DevExitLat, it doesn't send SET_SEL requests to the gadget. There
may be some hosts which may send SET_SEL requests even after seeing 0 in
the UxDevExitLat of BOS descriptor. To aviod U1/U2 entries for these type
of hosts, dwc3 controller can be programmed to reject those U1/U2 requests
by not enabling ACCEPTUxENA bits in DCTL register.

This patch updates the same.

Signed-off-by: Anurag Kumar Vulisha 
Signed-off-by: Claus H. Stovgaard 
Signed-off-by: Felipe Balbi

usb: dwc3: qcom: Use of_clk_get_parent_count()

2019-06-18T08:58:29+00:00

Use of_clk_get_parent_count() instead of open coding.

Signed-off-by: Kefeng Wang 
Signed-off-by: Felipe Balbi

usb: dwc3: Fix core validation in probe, move after clocks are enabled

2019-06-18T08:58:29+00:00

The required clocks needs to be enabled before the first register
access. After commit fe8abf332b8f ("usb: dwc3: support clocks and resets
for DWC3 core"), this happens when the dwc3_core_is_valid function is
called, but the mentioned commit adds that call in the wrong place,
before the clocks are enabled. So, move that call after the
clk_bulk_enable() to ensure the clocks are enabled and the reset
deasserted.

I detected this while, as experiment, I tried to move the clocks and resets
from the glue layer to the DWC3 core on a Samsung Chromebook Plus.

That was not detected before because, in most cases, the glue layer
initializes SoC-specific things and then populates the child "snps,dwc3"
with those clocks already enabled.

Fixes: b873e2d0ea1ef ("usb: dwc3: Do core validation early on probe")
Signed-off-by: Enric Balletbo i Serra 
Signed-off-by: Felipe Balbi

usb: dwc3: qcom: Improve error handling

2019-06-18T08:58:29+00:00

dwc3_qcom_clk_init() is called with of_count_phandle_with_args() as an
argument.  If of_count_phandle_with_args() returns an error, the number
of clocks will be a negative value and will lead to undefined behaviour.

Ensure we check for an error before attempting to blindly use the value.

Signed-off-by: Lee Jones 
Reviewed-by: Bjorn Andersson 
Signed-off-by: Felipe Balbi

usb: dwc3: qcom: Start USB in 'host mode' on the SDM845

2019-06-18T08:58:29+00:00

When booting with Device Tree, the current default boot configuration
table option, the request to boot via 'host mode' comes from the
'dr_mode' property.  A property of the same name can be used inside
ACPI tables too.  However it is missing from the SDM845's ACPI tables
so we have to supply this information using Platform Device Properties
instead.

This does not change the behaviour of any currently supported devices.
The property is only set on ACPI enabled platforms, thus for H/W
booting DT, unless a 'dr_mode' property is present, the default is
still OTG (On-The-Go) as per [0].  Any new ACPI devices added will
also be able to over-ride this implementation by providing a 'dr_mode'
property in their ACPI tables.  In cases where 'dr_mode' is omitted
from the tables AND 'host mode' should not be the default (very
unlikely), then we will have to add some way of choosing between them
at run time - most likely by ACPI HID.

[0] Documentation/devicetree/bindings/usb/generic.txt

Signed-off-by: Lee Jones 
Reviewed-by: Bjorn Andersson 
Signed-off-by: Felipe Balbi