linux.git/include/asm-powerpc/cputable.h, branch master

powerpc: Move include files to arch/powerpc/include/asm

2008-08-04T02:02:00+00:00

from include/asm-powerpc.  This is the result of a

mkdir arch/powerpc/include/asm
git mv include/asm-powerpc/* arch/powerpc/include/asm

Followed by a few documentation/comment fixups and a couple of places
where  was being used explicitly.  Of the latter only
one was outside the arch code and it is a driver only built for powerpc.

Signed-off-by: Stephen Rothwell 
Signed-off-by: Paul Mackerras

powerpc: Enable AT_BASE_PLATFORM aux vector

2008-07-25T05:44:39+00:00

Stash the first platform string matched by identify_cpu() in
powerpc_base_platform, and supply that to the ELF loader for the value
of AT_BASE_PLATFORM.

Signed-off-by: Nathan Lynch 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPAT

2008-07-15T02:24:57+00:00

Background from Maynard Johnson:
As of POWER6, a set of 32 common events is defined that must be
supported on all future POWER processors.  The main impetus for this
compat set is the need to support partition migration, especially from
processor P(n) to processor P(n+1), where performance software that's
running in the new partition may not be knowledgeable about processor
P(n+1).  If a performance tool determines it does not support the
physical processor, but is told (via the
PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports
the notion of the PMU compat set, then the performance tool can
surface just those events to the user of the tool.

PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at
least this basic subset of events which is compatible across POWER
processor lines.

Signed-off-by: Nathan Lynch 
Signed-off-by: Benjamin Herrenschmidt

powerpc/mm: Add SAO Feature bit to the cputable

2008-07-09T06:30:45+00:00

Add the CPU feature bit for the new Strong Access Ordering
facility of Power7

Signed-off-by: Dave Kleikamp 
Signed-off-by: Joel Schopp 
Signed-off-by: Benjamin Herrenschmidt

powerpc: Fixup lwsync at runtime

2008-07-03T06:58:10+00:00

To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
at runtime.  On e500v1/v2 lwsync causes an illop so we need to patch up
the code.  We default to 'sync' since that is always safe and if the cpu
is capable we will replace 'sync' with 'lwsync'.

We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
needed.  This flag could be moved elsewhere since we dont really use it
for the normal CPU_FTR purpose.

Finally we only store the relative offset in the fixup section to keep it
as small as possible rather than using a full fixup_entry.

Signed-off-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc: Add VSX CPU feature

2008-07-01T01:28:47+00:00

Add a VSX CPU feature.  Also add code to detect if VSX is available
from the device tree.

Signed-off-by: Michael Neuling 
Signed-off-by: Joel Schopp 
Signed-off-by: Paul Mackerras

powerpc: Consolidate CPU and firmware feature fixup macros

2008-07-01T01:28:25+00:00

The CPU and firmware feature fixup macros are currently spread across
three files, firmware.h, cputable.h and asm-compat.h.  Consolidate them
into their own file, feature-fixups.h

Signed-off-by: Michael Ellerman 
Acked-by: Kumar Gala 
Signed-off-by: Paul Mackerras

powerpc: Don't export asm/asm-compat.h to userspace

2008-07-01T01:28:09+00:00

asm/asm-compat.h doesn't seem to be intended for userspace usage.

Signed-off-by: Adrian Bunk 
Signed-off-by: Paul Mackerras

powerpc: Add cputable entry for POWER7

2008-06-30T12:31:11+00:00

Add a cputable entry for the POWER7 processor.

Also tell firmware that we know about POWER7.

Signed-off-by: Michael Neuling 
Signed-off-by: Joel Schopp 
Signed-off-by: Paul Mackerras

powerpc/e500mc: flush L2 on NAP for e500mc

2008-06-26T06:49:03+00:00

If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala