linux.git/include/drm/bridge, branch v6.6.132

drm: bridge: samsung-dsim: Fix waiting for empty cmd transfer FIFO on older Exynos

2023-11-20T10:59:08+00:00

[ Upstream commit 15f389da11257b806da75a070cfa41ca0cc15aae ]

Samsung DSIM used in older Exynos SoCs (like Exynos 4210, 4x12, 3250)
doesn't report empty level of packer header FIFO. In case of those SoCs,
use the old way of waiting for empty command tranfsfer FIFO, removed
recently by commit 14806c641582 ("drm: bridge: samsung-dsim: Drain command transfer FIFO before transfer").

Fixes: 14806c641582 ("drm: bridge: samsung-dsim: Drain command transfer FIFO before transfer")
Signed-off-by: Marek Szyprowski 
Reviewed-by: Marek Vasut 
Signed-off-by: Robert Foss 
Link: https://patchwork.freedesktop.org/patch/msgid/20230809145641.3213210-1-m.szyprowski@samsung.com
Signed-off-by: Sasha Levin

drm/bridge: dw-hdmi: change YUV420 selection logic at clock setup

2023-06-27T07:51:31+00:00

Right now clocking value selection code is prioritising RGB, YUV444 modes
over YUV420 for HDMI2 sinks. However, because of the bus format selection
procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always
be picked during the drm bridge chain check stage.

Later on dw_hdmi_setup will configure a colour space based on the bus
format that doesn't match the pixel value we had calculated as described
above.

Fix it by bringing back dw-hdmi bus format check when picking the right
pixel clock.

Signed-off-by: Adrián Larumbe 
Acked-by: Neil Armstrong 
Signed-off-by: Neil Armstrong 
Link: https://patchwork.freedesktop.org/patch/msgid/6230bfae2cd97cf6527fc62ba5c850464919ccf8.1687702042.git.adrian.larumbe@collabora.com

drm: bridge: samsung-dsim: Dynamically configure DPHY timing

2023-05-26T07:20:41+00:00

The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too.  To facilitate this, we need to cache the hs_clock
based on what is generated from the PLL.

The phy_mipi_dphy_get_default_config_for_hsclk function
configures the DPHY timings in pico-seconds, and a small macro
converts those timings into clock cycles based on the hs_clk.

Signed-off-by: Adam Ford 
Signed-off-by: Lucas Stach 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Michael Walle 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
Signed-off-by: Neil Armstrong 
Link: https://patchwork.freedesktop.org/patch/msgid/20230526030559.326566-6-aford173@gmail.com

drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]

2023-05-26T07:20:40+00:00

According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect.  This information was contradicted in other
parts of the mini, nano and plus manuals.  After reaching out to my
NXP Rep, when confronting him about discrepencies in the Nano manual,
he responded with:
 "Yes it is definitely wrong, the one that is part
  of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P,
  PMS_M and PMS_S is not correct. I will report this to Doc team,
  the one customer should be take into account is the Table 13-40
  DPHY PLL Parameters and the Note above."

These updated values also match what is used in the NXP downstream
kernel.

To fix this, make new variables to hold the min and max values of m
and the minimum value of VCO_out, and update the PMS calculator to
use these new variables instead of using hard-coded values to keep
the backwards compatibility with other parts using this driver.

Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support")
Signed-off-by: Adam Ford 
Reviewed-by: Lucas Stach 
Tested-by: Chen-Yu Tsai 
Tested-by: Frieder Schrempf 
Reviewed-by: Frieder Schrempf 
Tested-by: Marek Szyprowski 
Reviewed-by: Jagan Teki 
Tested-by: Jagan Teki  # imx8mm-icore
Signed-off-by: Neil Armstrong 
Link: https://patchwork.freedesktop.org/patch/msgid/20230526030559.326566-3-aford173@gmail.com

drm: bridge: samsung-dsim: Implement support for clock/data polarity swap

2023-05-22T13:37:18+00:00

Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.

This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.

Signed-off-by: Marek Vasut 
Signed-off-by: Fabio Estevam 
Reviewed-by: Jagan Teki 
Signed-off-by: Neil Armstrong 
Link: https://patchwork.freedesktop.org/patch/msgid/20230514114625.98372-2-festevam@gmail.com

drm: bridge: samsung-dsim: Add i.MX8M Plus support

2023-03-28T00:05:41+00:00

Add extras to support i.MX8M Plus. The main change is the removal of
HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise
the implementation of this IP in i.MX8M Plus is very much compatible
with the i.MX8M Mini/Nano one.

Reviewed-by: Marek Vasut 
Reviewed-by: Frieder Schrempf 
Acked-by: Robert Foss 
Signed-off-by: Marek Vasut 
Signed-off-by: Jagan Teki 
Tested-by: Marek Szyprowski 
Signed-off-by: Inki Dae

drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge

2023-03-28T00:05:41+00:00

Samsung MIPI DSIM controller is common DSI IP that can be used in various
SoCs like Exynos, i.MX8M Mini/Nano.

In order to access this DSI controller between various platform SoCs,
the ideal way to incorporate this in the drm stack is via the drm bridge
driver.

We already have a consolidated code for supporting component and bridge
based DRM drivers, so keep the exynos component based code in existing
exynos_drm_dsi.c and move generic bridge code as part of samsung-dsim.c

Tested-by: Marek Szyprowski 
Reviewed-by: Marek Vasut 
Signed-off-by: Marek Szyprowski 
Signed-off-by: Jagan Teki 
Signed-off-by: Inki Dae

drm: bridge: dw_hdmi: Audio: Add General Parallel Audio (GPA) driver

2022-04-19T16:23:48+00:00

General Parallel Audio (GPA) interface is one of the supported
audio interface for synopsys HDMI module, which has verified for
i.MX8MPlus platform.
This is initial version for GPA.

Signed-off-by: Shengjiu Wang 
Signed-off-by: Sandor Yu 
Reviewed-by: Neil Armstrong 
Signed-off-by: Robert Foss 
Link: https://patchwork.freedesktop.org/patch/msgid/f21ba3e8c4d9d028ac74c6f3c588ddbffe739399.1649989179.git.Sandor.yu@nxp.com

drm: bridge: dw_hdmi: add reset function for PHY GEN1

2022-04-19T16:19:03+00:00

PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2,
and active low reset control for PHY GEN1.

Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset.
Add dw_hdmi_phy_gen1_reset function for PHY GEN1.

Signed-off-by: Sandor Yu 
Reviewed-by: Neil Armstrong 
Acked-by: Jernej Skrabec 
Signed-off-by: Robert Foss 
Link: https://patchwork.freedesktop.org/patch/msgid/e0b3be2d63fe3e95246fb8b8b0dcd57415b29e04.1649989179.git.Sandor.yu@nxp.com

drm/bridge/synopsys: dsi: extend the prototype of mode_valid()

2022-01-04T11:53:59+00:00

To evaluate the validity of a video mode, some additional internal
value has to be passed to the platform implementation.

Extend the prototype of mode_valid().

Signed-off-by: Antonio Borneo 
Reviewed-by: Philippe Cornu 
Signed-off-by: Robert Foss 
Link: https://patchwork.freedesktop.org/patch/msgid/20211218215055.212421-2-antonio.borneo@foss.st.com