linux.git/include/dt-bindings/reset/starfive,jh7110-crg.h, branch v6.18.22

dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator

2023-07-19T17:08:00+00:00

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt 
Reviewed-by: Emil Renner Berthing 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

2023-07-19T17:08:00+00:00

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt 
Reviewed-by: Emil Renner Berthing 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator

2023-07-19T17:08:00+00:00

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt 
Reviewed-by: Emil Renner Berthing 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Xingyu Wu 
Signed-off-by: Conor Dooley

dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator

2023-04-05T14:43:24+00:00

Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley 
Reviewed-by: Rob Herring 
Reviewed-by: Emil Renner Berthing 
Signed-off-by: Emil Renner Berthing 
Signed-off-by: Hal Feng 
Signed-off-by: Conor Dooley

dt-bindings: clock: Add StarFive JH7110 system clock and reset generator

2023-04-05T14:43:15+00:00

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley 
Reviewed-by: Rob Herring 
Reviewed-by: Emil Renner Berthing 
Signed-off-by: Emil Renner Berthing 
Signed-off-by: Hal Feng 
Signed-off-by: Conor Dooley