[ Upstream commit f47c1b77d0a2a9c0d49ec14302e74f933398d1a3 ]
The clk_save_context() and clk_restore_context() helpers are only
implemented by the Common Clock Framework. They are not available when
using legacy clock frameworks. Dummy implementations are provided, but
only if no clock support is available at all.
Hence when CONFIG_HAVE_CLK=y, but CONFIG_COMMON_CLK is not enabled:
m68k-linux-gnu-ld: drivers/net/phy/air_en8811h.o: in function `en8811h_resume':
air_en8811h.c:(.text+0x83e): undefined reference to `clk_restore_context'
m68k-linux-gnu-ld: drivers/net/phy/air_en8811h.o: in function `en8811h_suspend':
air_en8811h.c:(.text+0x856): undefined reference to `clk_save_context'
Fix this by moving forward declarations and dummy implementions from the
HAVE_CLK to the COMMON_CLK section.
Fixes: 8b95d1ce3300c411 ("clk: Add functions to save/restore clock context en-masse")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202511301553.eaEz1nEW-lkp@intel.com/
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
The COMMON_CLK config is not enabled in some of the architectures.
This causes below build issues:
pwm-rz-mtu3.c:(.text+0x114):
undefined reference to `clk_rate_exclusive_put'
pwm-rz-mtu3.c:(.text+0x32c):
undefined reference to `clk_rate_exclusive_get'
Fix these issues by moving clk_rate_exclusive_{get,put} inside COMMON_CLK
code block, as clk.c is enabled by COMMON_CLK.
Fixes: 55e9b8b7b806 ("clk: add clk_rate_exclusive api")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/all/202307251752.vLfmmhYm-lkp@intel.com/
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20230725175140.361479-1-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk_has_parent() doesn't modify the clocks being passed, so let's make it const. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-21-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When a driver keeps a clock prepared (or enabled) during the whole lifetime of the driver, these helpers allow to simplify the drivers. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <aardelean@deviqon.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220520075737.758761-4-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Make use of "Context:" and "Return:". Mention that the clk is not to be expected to be prepared, previously only not being enabled was mentioned which probably dates from the times when the concept of clk preparation wasn't invented yet. Also describe devm_clk_get_optional() fully instead of just referencing devm_clk_get(). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20220520075737.758761-2-u.kleine-koenig@pengutronix.de Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In order to reset the range on a clock, we need to call clk_set_rate_range with a minimum of 0 and a maximum of ULONG_MAX. Since it's fairly inconvenient, let's introduce a clk_drop_range() function that will do just this. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220225143534.405820-8-maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull clk updates from Stephen Boyd:
"This is all driver updates, the majority of which is a bunch of new
Qualcomm clk drivers that dominate the diffstat because we add support
for six SoCs from that particular vendor.
The other big change is the removal of various clk drivers that are no
longer used now that the kernel is dropping support for those SoCs.
Beyond that there's the usual non-critical fixes for existing drivers
and a good number of patches from Lee Jones that cleanup a bunch of
W=1 enabled builds.
Removed Drivers:
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
New Drivers:
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- GPU clks for Qualcomm SDM660/SDM630
Updates:
- Video clk fixups on Qualcomm SM8250
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid
glitches at boot
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
- Amlogic pll driver fixup
- Amlogic meson8b clock controller dt support clean up
- Remove mipi clk from the Amlogic axg clock controller
- New Rockchip rk3368 clock ids related to camera input
- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
reparenting
- A series from Liu Ying that adds some SCU clocks support for
i.MX8qxp DC0/MIPI-LVDS subsystems
- A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
and clkout1/2 support for i.MX8MM/MN
- Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U
- Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs
- Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial
(HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA
(SYS-DMAC) clocks on Renesas R-Car V3U
- Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs
- Allwinner H616 SoC clk support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (171 commits)
clk: mstar: msc313-mpll: Fix format specifier
clk: mstar: Allow MStar clk drivers to be compile tested
clk: qoriq: use macros to generate pll_mask
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: gcc-sm8350: add gdsc
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
clk: mstar: MStar/SigmaStar MPLL driver
...
The clock API splits its interface into sleepable ant atomic contexts: - clk_prepare/clk_unprepare for stuff that might sleep - clk_enable_clk_disable for anything that may be done in atomic context The code handling runtime PM for clocks only calls clk_disable() on suspend requests, and clk_enable on resume requests. This means that runtime PM with clock providers that only have the prepare/unprepare methods implemented is basically useless. Many clock implementations can't accommodate atomic contexts. This is often the case when communication with the clock happens through another subsystem like I2C or SCMI. Let's make the clock PM code useful with such clocks by safely invoking clk_prepare/clk_unprepare upon resume/suspend requests. Of course, when such clocks are registered with the PM layer then pm_runtime_irq_safe() can't be used, and neither pm_runtime_suspend() nor pm_runtime_resume() may be invoked in atomic context. For clocks that do implement the enable and disable methods then everything just works as before. A note on sparse: According to https://lwn.net/Articles/109066/ there are things that sparse can't cope with. In particular, pm_clk_op_lock() and pm_clk_op_unlock() may or may not lock/unlock psd->lock depending on some runtime condition. To work around that we tell it the lock is always untaken for the purpose of static analisys. Thanks to Naresh Kamboju for reporting issues with the initial patch. Signed-off-by: Nicolas Pitre <npitre@baylibre.com> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Fix kernel-doc notation for 2 functions so that the generated
html is correct. Currently it skips all text between the
':' and the '-', so "[un]register a clock rate" is missing.
Fixes: 86bcfa2e87c4 ("clk: add pr_debug & kerneldoc around clk notifiers")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20210107023304.24442-1-rdunlap@infradead.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw * clk-doc: clk: fix a kernel-doc markup * clk-qcom: (27 commits) clk: qcom: rpmh: add support for SM8350 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8350 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks clk: qcom: Add GDSC support for SDX55 GCC dt-bindings: clock: Add GDSC in SDX55 GCC clk: qcom: Add support for SDX55 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX55 clk: qcom: Add SDX55 GCC support dt-bindings: clock: Add SDX55 GCC clock bindings clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic" clk: qcom: rpmh: Add CE clock on sdm845. dt-bindings: clock: Add entry for crypto engine RPMH clock resource clk: qcom: dispcc-sm8250: handle MMCX power domain clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init() clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks dt-bindings: clock: Add support for LPASS Always ON Controller ... * clk-simplify: clk: remove unneeded dead-store initialization * clk-hw: clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash * clk-renesas: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI * clk-samsung: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210