<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/include/soc/sifive, branch v6.12.80</title>
<subtitle>Clone of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git</subtitle>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/'/>
<entry>
<title>soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.</title>
<updated>2022-10-13T18:06:51+00:00</updated>
<author>
<name>Greentime Hu</name>
<email>greentime.hu@sifive.com</email>
</author>
<published>2022-09-13T06:18:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=ca120a79cf5a3323172c82e77efd70ae10d120ef'/>
<id>ca120a79cf5a3323172c82e77efd70ae10d120ef</id>
<content type='text'>
Since composable cache may be L3 cache if there is a L2 cache, we should
use its original name composable cache to prevent confusion.

There are some new lines were generated due to adding the compatible
"sifive,ccache0" into ID table and indent requirement.

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well.

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Co-developed-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since composable cache may be L3 cache if there is a L2 cache, we should
use its original name composable cache to prevent confusion.

There are some new lines were generated due to adding the compatible
"sifive,ccache0" into ID table and indent requirement.

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well.

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Co-developed-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: move sifive_l2_cache.h to include/soc</title>
<updated>2020-01-12T18:12:44+00:00</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2020-01-08T06:09:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.exis.tech/linux.git/commit/?id=13cf4cf030183dd9a8731f3fe32456e83b6c7b68'/>
<id>13cf4cf030183dd9a8731f3fe32456e83b6c7b68</id>
<content type='text'>
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
moves the sifive L2 cache driver to driver/soc. It did not move the
header file along with the driver. Therefore this patch moves the header
file to driver/soc

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
[paul.walmsley@sifive.com: updated to fix the include guard]
Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc")
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</pre>
</div>
</content>
</entry>
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