Merge tag 'hwmon-for-v7.2-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/groec...

[linux.git] / arch / arm64 / kernel / fpsimd.c

diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 25dc5afe9ba0c8923acda6f815541d5bd984cef7..e7f1682a3059b5d083a4d62c611e9e2e781797ad 100644 (file)
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1355,6 +1355,7 @@ void do_sve_acc(unsigned long esr, struct pt_regs *regs)
  * SME/CME erratum handling.
  */
 static cpumask_t sme_dvmsync_cpus;
+cpumask_t sme_active_cpus;
 
 /*
  * These helpers are only called from non-preemptible contexts, so
@@ -1368,13 +1369,15 @@ void sme_set_active(void)
                return;
 
        cpumask_set_cpu(cpu, mm_cpumask(current->mm));
+       cpumask_set_cpu(cpu, &sme_active_cpus);
 
        /*
         * A subsequent (post ERET) SME access may use a stale address
         * translation. On C1-Pro, a TLBI+DSB on a different CPU will wait for
-        * the completion of cpumask_set_cpu() above as it appears in program
-        * order before the SME access. The post-TLBI+DSB read of mm_cpumask()
-        * will lead to the IPI being issued.
+        * the completion of the cpumask_set_cpu() operations above as they
+        * appear in program order before the SME access. The post-TLBI+DSB
+        * read of mm_cpumask() or sme_active_cpus will lead to the IPI being
+        * issued.
         *
         * https://lore.kernel.org/r/ablEXwhfKyJW1i7l@J2N7QTR9R3
         */
@@ -1392,6 +1395,7 @@ void sme_clear_active(void)
         * completed on entering EL1.
         */
        cpumask_clear_cpu(cpu, mm_cpumask(current->mm));
+       cpumask_clear_cpu(cpu, &sme_active_cpus);
 }
 
 static void sme_dvmsync_ipi(void *unused)