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clk: socfpga: agilex: implement l3_main_free_clk
authorAdrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Fri, 22 May 2026 09:02:54 +0000 (17:02 +0800)
committerDinh Nguyen <dinguyen@kernel.org>
Tue, 26 May 2026 02:46:56 +0000 (21:46 -0500)
commit1e7f56205813a2c48cdb3e9a4b0a24f49fd9a548
tree5c8157e0bf0c90a93f321efa3cc2144f9143bfa0tree | snapshot
parent254f49634ee16a731174d2ae34bc50bd5f45e731commit | diff
clk: socfpga: agilex: implement l3_main_free_clk

The AGILEX_L3_MAIN_FREE_CLK is defined in the dt-bindings header but
was never implemented in the clock driver. Per the Agilex TRM,
l3_main_free_clk has no divider or mux and is a fixed 1:1 derivative
of noc_free_clk that clocks most of the interconnect datapath.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
drivers/clk/socfpga/clk-agilex.c diff | blob | history
Upstream Linux kernel source code