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| author | Fabrice Gasnier <fabrice.gasnier@foss.st.com> | 2022-11-23 14:36:52 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-03-11 16:26:50 +0100 |
| commit | e5f404943618adeed202c4dbd67814055d0f9c0d (patch) | |
| tree | 651436c94bb5cde860449193a9c1d8789840201b | |
| parent | 668a1a9868c3bf2f885e78257a9bd0017ea2fa6d (diff) | |
| download | linux-e5f404943618adeed202c4dbd67814055d0f9c0d.tar.gz linux-e5f404943618adeed202c4dbd67814055d0f9c0d.tar.bz2 linux-e5f404943618adeed202c4dbd67814055d0f9c0d.zip | |
pwm: stm32-lp: fix the check on arr and cmp registers update
[ Upstream commit 3066bc2d58be31275afb51a589668f265e419c37 ]
The ARR (auto reload register) and CMP (compare) registers are
successively written. The status bits to check the update of these
registers are polled together with regmap_read_poll_timeout().
The condition to end the loop may become true, even if one of the
register isn't correctly updated.
So ensure both status bits are set before clearing them.
Fixes: e70a540b4e02 ("pwm: Add STM32 LPTimer PWM driver")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | drivers/pwm/pwm-stm32-lp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 3f2e4ef695d7..ba0aa3b8076b 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -127,7 +127,7 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* ensure CMP & ARR registers are properly written */ ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, - (val & STM32_LPTIM_CMPOK_ARROK), + (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); |