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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-01-06 17:53:31 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-03-19 13:44:43 +0100 |
| commit | 6493c6aa8b4467c587444aa4b12805f6cc7307c9 (patch) | |
| tree | 50824f72013936e27a52f1cde8e565aace36dfce | |
| parent | c5c8c649fee0833c69c0f768cc3e9531c7701b3b (diff) | |
| download | linux-6493c6aa8b4467c587444aa4b12805f6cc7307c9.tar.gz linux-6493c6aa8b4467c587444aa4b12805f6cc7307c9.tar.bz2 linux-6493c6aa8b4467c587444aa4b12805f6cc7307c9.zip | |
arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 07c099b4ed5b..1e0c9415bfcd 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -476,7 +476,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = <0 93 4>; phys = <&usbphy0>; @@ -489,7 +489,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = <0 94 4>; phys = <&usbphy0>; |