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| author | Gabor Juhos <j4g8y7@gmail.com> | 2024-05-08 22:34:14 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-07-11 12:49:19 +0200 |
| commit | 66b6da0cc64c5b805f54a654dc29a732b092d2f0 (patch) | |
| tree | ece40eff7a28c17675fb3c2c73b3511c7473e05f | |
| parent | 0fcb94e0ee89770c794eb5405b13284e4bb72d91 (diff) | |
| download | linux-66b6da0cc64c5b805f54a654dc29a732b092d2f0.tar.gz linux-66b6da0cc64c5b805f54a654dc29a732b092d2f0.tar.bz2 linux-66b6da0cc64c5b805f54a654dc29a732b092d2f0.zip | |
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
[ Upstream commit 5a33a64524e6381c399e5e42571d9363ffc0bed4 ]
The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.
Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.
Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 5cf862b0bb62..85aa089650ea 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2510,6 +2510,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> ALPHA_BITWIDTH); + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), + PLL_ALPHA_EN, PLL_ALPHA_EN); + regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); /* Wait five micro seconds or more */ |