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| author | Dave Jiang <dave.jiang@intel.com> | 2025-10-22 13:30:52 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-11-03 09:29:00 -0700 |
| commit | d6602e25819dea2c239972e98e09ba5db4aebd22 (patch) | |
| tree | 1ed30d787c74a92615efe0a9db644b4a64abfed6 /Documentation/ABI | |
| parent | f0c5d3bc2830f04a72087f45d15807943eabfa10 (diff) | |
| download | linux-d6602e25819dea2c239972e98e09ba5db4aebd22.tar.gz linux-d6602e25819dea2c239972e98e09ba5db4aebd22.tar.bz2 linux-d6602e25819dea2c239972e98e09ba5db4aebd22.zip | |
cxl/region: Add support to indicate region has extended linear cache
Add a region sysfs attribute to show the size of the extended linear
cache if there is any. The attribute is invisible when the cache
size is 0, which indicates it does not exist.
Moved the cxl_region_visible() location in order to pick up the
new sysfs attribute definition.
[ dj: Fixed spelling errors noted by Benjamin ]
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20251022203052.4078527-1-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'Documentation/ABI')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-cxl | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 6b4e8c7a963d..c80a1b5a03db 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -496,8 +496,17 @@ Description: changed, only freed by writing 0. The kernel makes no guarantees that data is maintained over an address space freeing event, and there is no guarantee that a free followed by an allocate - results in the same address being allocated. + results in the same address being allocated. If extended linear + cache is present, the size indicates extended linear cache size + plus the CXL region size. +What: /sys/bus/cxl/devices/regionZ/extended_linear_cache_size +Date: October, 2025 +KernelVersion: v6.19 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The size of extended linear cache, if there is an extended + linear cache. Otherwise the attribute will not be visible. What: /sys/bus/cxl/devices/regionZ/mode Date: January, 2023 |