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authorLinus Torvalds <torvalds@linux-foundation.org>2025-12-09 06:31:47 +0900
committerLinus Torvalds <torvalds@linux-foundation.org>2025-12-09 06:31:47 +0900
commit0623fdf30b1105c22f58baeeca954c803bdf5f8b (patch)
treece9cda873cc3dae135b65c3789e11f5044743585 /Documentation/devicetree
parentfeb06d2690bb826fd33798a99ce5cff8d07b38f9 (diff)
parent716311dad200edf01a3776b62466571dfd217106 (diff)
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Merge tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul: "Core: - Drop Kishon as maintainer, thanks to him for helping, move to credits and add Neil to help with reviews. - Add new phy_notify_stat to notify phy from controllers during the runtime transitions and usage in samsung phy New hardware support: - Renesas RZ/G3E USB3.0 driver - NXP Support TJA1048/TJA1051 CAN phy - Rockchip support for rk3506 dsi dphy - Qualcomm Glymur QMP PCIe PHY support Updates: - PM support for rcar-gen3-usb2 driver - Samsung HDMI/eDP Transmitter Combo PHY updates - Freescale imx8mq support for alternate reference clock" * tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits) MAINTAINERS: phy: Add Neil Armstrong as reviewers for phy subsystem MAINTAINERS: phy: Move Kishon Vijay Abraham I to credits phy: fsl-imx8mq-usb: support alternate reference clock dt-bindings: phy: imx8mq-usb: add alternate reference clock phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode phy: ti: gmii-sel: Add a sanity check on the phy_id phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY phy: qcom-qmp: pcs: Add v8.50 register offsets dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Restrict resets per each device phy: freescale: Initialize priv->lock phy: renesas: Remove unneeded semicolons phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE phy: qcom: qmp-combo: get the USB3 & DisplayPort lanes mapping from DT dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562 phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528 phy: renesas: rcar-gen3-usb2: Add suspend/resume support ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml7
-rw-r--r--Documentation/devicetree/bindings/phy/mediatek,tphy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml11
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml69
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml63
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml69
8 files changed, 217 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
index f9cffbb2df07..8a00a6c58edd 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.yaml
@@ -27,11 +27,16 @@ properties:
const: 0
clocks:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: PHY configuration clock
+ - description: Alternate PHY reference clock
clock-names:
+ minItems: 1
items:
- const: phy
+ - const: alt
power-domains:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b2218c151939..ff5c77ef1176 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -80,6 +80,7 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt6893-tphy
- mediatek,mt7629-tphy
+ - mediatek,mt7981-tphy
- mediatek,mt7986-tphy
- mediatek,mt8183-tphy
- mediatek,mt8186-tphy
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 119b4ff36dbd..48bd11410e8c 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
+ - qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,qcs8300-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
@@ -178,6 +179,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,sa8775p-qmp-gen4x2-pcie-phy
- qcom,sa8775p-qmp-gen4x4-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
@@ -213,17 +215,26 @@ allOf:
compatible:
contains:
enum:
+ - qcom,glymur-qmp-gen5x4-pcie-phy
- qcom,sm8550-qmp-gen4x2-pcie-phy
- qcom,sm8650-qmp-gen4x2-pcie-phy
+ - qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
+ - qcom,x1p42100-qmp-gen4x4-pcie-phy
then:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
+ else:
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ maxItems: 1
- if:
properties:
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index c8bc512df08b..e0ec45b96bf5 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -78,10 +78,77 @@ properties:
ports:
$ref: /schemas/graph.yaml#/properties/ports
+
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
description: Output endpoint of the PHY
+ unevaluatedProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ description: Display Port Output lanes of the PHY when used with static mapping,
+ The entry index is the DP lanes index, and the number is the PHY
+ signal in the order RX0, TX0, TX1, RX1.
+ unevaluatedProperties: false
+
+ properties:
+ # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 4
+ oneOf:
+ - items: # DisplayPort 1 lane, normal orientation
+ - const: 3
+ - items: # DisplayPort 1 lane, flipped orientation
+ - const: 0
+ - items: # DisplayPort 2 lanes, normal orientation
+ - const: 3
+ - const: 2
+ - items: # DisplayPort 2 lanes, flipped orientation
+ - const: 0
+ - const: 1
+ - items: # DisplayPort 4 lanes, normal orientation
+ - const: 3
+ - const: 2
+ - const: 1
+ - const: 0
+ - items: # DisplayPort 4 lanes, flipped orientation
+ - const: 0
+ - const: 1
+ - const: 2
+ - const: 3
+ required:
+ - data-lanes
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ description: USB Output lanes of the PHY when used with static mapping.
+ The entry index is the USB3 lane in the order TX then RX, and the
+ number is the PHY signal in the order RX0, TX0, TX1, RX1.
+ unevaluatedProperties: false
+
+ properties:
+ # Static lane mappings are mutually exclusive with typec-mux/orientation-mux
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ oneOf:
+ - items: # USB3, normal orientation
+ - const: 1
+ - const: 0
+ - items: # USB3, flipped orientation
+ - const: 2
+ - const: 3
+
+ required:
+ - data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
diff --git a/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
new file mode 100644
index 000000000000..b86dc7a291a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G3E USB 3.0 PHY
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ const: renesas,r9a09g047-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: USB 2.0 PHY reference clock
+ - description: USB 3.0 PHY reference clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: core
+ - const: ref_alt_clk_p
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+
+ usb-phy@15870000 {
+ compatible = "renesas,r9a09g047-usb3-phy";
+ reg = <0x15870000 0x10000>;
+ clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
+ clock-names = "pclk", "core", "ref_alt_clk_p";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xaa>;
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 179cb4bfc424..2bbec8702a1e 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -118,6 +118,7 @@ allOf:
contains:
enum:
- renesas,usb2-phy-r9a09g057
+ - renesas,usb2-phy-r9a08g045
- renesas,rzg2l-usb2-phy
then:
properties:
diff --git a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
index 46e64fa293d5..83e7c825860c 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml
@@ -18,6 +18,7 @@ properties:
- rockchip,px30-dsi-dphy
- rockchip,rk3128-dsi-dphy
- rockchip,rk3368-dsi-dphy
+ - rockchip,rk3506-dsi-dphy
- rockchip,rk3568-dsi-dphy
- rockchip,rv1126-dsi-dphy
diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
index 138923ffedfe..c686d06f5f56 100644
--- a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
@@ -23,16 +23,26 @@ properties:
- enum:
- ti,tcan1042
- ti,tcan1043
+ - nxp,tja1048
+ - nxp,tja1051
+ - nxp,tja1057
- nxp,tjr1443
'#phy-cells':
- const: 0
+ enum: [0, 1]
- standby-gpios:
+ silent-gpios:
description:
- gpio node to toggle standby signal on transceiver
+ gpio node to toggle silent signal on transceiver
maxItems: 1
+ standby-gpios:
+ description:
+ gpio node to toggle standby signal on transceiver. For two Items, item 1
+ is for stbn1, item 2 is for stbn2.
+ minItems: 1
+ maxItems: 2
+
enable-gpios:
description:
gpio node to toggle enable signal on transceiver
@@ -54,6 +64,59 @@ required:
- compatible
- '#phy-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - nxp,tjr1443
+ - ti,tcan1042
+ - ti,tcan1043
+ then:
+ properties:
+ '#phy-cells':
+ const: 0
+ silent-gpios: false
+ standby-gpios:
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nxp,tja1048
+ then:
+ properties:
+ '#phy-cells':
+ const: 1
+ enable-gpios: false
+ silent-gpios: false
+ standby-gpios:
+ minItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nxp,tja1051
+ then:
+ properties:
+ '#phy-cells':
+ const: 0
+ standby-gpios: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nxp,tja1057
+ then:
+ properties:
+ '#phy-cells':
+ const: 0
+ enable-gpios: false
+ standby-gpios: false
+
additionalProperties: false
examples: