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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-01-14 12:54:52 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-01-14 12:29:30 +0000 |
| commit | a9ff94477836cb43d94efbd9a851213944800177 (patch) | |
| tree | 5a805a10862227e2a6330df0df3d66fbf88a89ff /arch/arm/include | |
| parent | 961d234779867695a7724fd4fb0a5a1bd3d4ccab (diff) | |
| download | linux-a9ff94477836cb43d94efbd9a851213944800177.tar.gz linux-a9ff94477836cb43d94efbd9a851213944800177.tar.bz2 linux-a9ff94477836cb43d94efbd9a851213944800177.zip | |
ARM: 9433/2: implement cacheinfo support
On ARMv7 / v7m machines read CTR and CLIDR registers to provide
information regarding the cache topology. Earlier machines should
describe full cache topology in the device tree.
Note, this follows the ARM64 cacheinfo support and provides only minimal
support required to bootstrap cache info. All useful properties should
be decribed in Device Tree.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index e3ea34558ada..ecbc100d22a5 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -26,4 +26,10 @@ #define __read_mostly __section(".data..read_mostly") +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +int cache_line_size(void); +#endif +#endif + #endif |