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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-06-20 17:26:42 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-06-27 10:44:24 +0200 |
| commit | a5c05453a13ab324ad8719e8a23dfb6af01f3652 (patch) | |
| tree | d18ef9dcf6d3c8789003228ee29a9a8813b2bfd9 /arch/mips/bmips | |
| parent | 7c48090af524410fe72754be5f4cfd92d9487957 (diff) | |
| download | linux-a5c05453a13ab324ad8719e8a23dfb6af01f3652.tar.gz linux-a5c05453a13ab324ad8719e8a23dfb6af01f3652.tar.bz2 linux-a5c05453a13ab324ad8719e8a23dfb6af01f3652.zip | |
mips: bmips: rework and cache CBR addr handling
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
with legacy brcm47xx/brcm63xx and generic BMIPS target.
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/bmips')
| -rw-r--r-- | arch/mips/bmips/dma.c | 2 | ||||
| -rw-r--r-- | arch/mips/bmips/setup.c | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd7..2bc9c0d4402f 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c287..6dd166c3d643 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,6 +34,9 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; + extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; @@ -111,7 +114,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +147,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); |