diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-29 10:36:01 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-11-29 10:36:01 -0800 |
| commit | 63c81af15cf8e64045e8ec55991363ef569a267a (patch) | |
| tree | dc7c136a756dd22e9934d8f1a355f0216202c157 /arch/mips/boot/dts/mobileye/eyeq5.dtsi | |
| parent | 9d5daef3b3a67535825dcdf1bfe078fdbada5606 (diff) | |
| parent | 4fbd66d8254cedfd1218393f39d83b6c07a01917 (diff) | |
| download | linux-63c81af15cf8e64045e8ec55991363ef569a267a.tar.gz linux-63c81af15cf8e64045e8ec55991363ef569a267a.tar.bz2 linux-63c81af15cf8e64045e8ec55991363ef569a267a.zip | |
Merge tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- fix for loongson64 device tree
- add SPI nand to realtek device tree
- change clock tree for mobileye
* tag 'mips_6.13_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: Loongson64: DTS: Really fix PCIe port nodes for ls7a
mips: dts: realtek: Add SPI NAND controller
MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks
MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
Diffstat (limited to 'arch/mips/boot/dts/mobileye/eyeq5.dtsi')
| -rw-r--r-- | arch/mips/boot/dts/mobileye/eyeq5.dtsi | 30 |
1 files changed, 24 insertions, 6 deletions
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 0708771c193d..5d73e8320b8e 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include <dt-bindings/interrupt-controller/mips-gic.h> -#include "eyeq5-clocks.dtsi" +#include <dt-bindings/clock/mobileye,eyeq5-clk.h> / { #address-cells = <2>; @@ -17,7 +17,7 @@ device_type = "cpu"; compatible = "img,i6500"; reg = <0>; - clocks = <&core0_clk>; + clocks = <&olb EQ5C_CPU_CORE0>; }; }; @@ -64,6 +64,24 @@ #interrupt-cells = <1>; }; + xtal: xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <30000000>; + }; + + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; + soc: soc { #address-cells = <2>; #size-cells = <2>; @@ -76,7 +94,7 @@ reg-io-width = <4>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&occ_periph>; + clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names = "uartclk", "apb_pclk"; resets = <&olb 0 10>; pinctrl-names = "default"; @@ -89,7 +107,7 @@ reg-io-width = <4>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&occ_periph>; + clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names = "uartclk", "apb_pclk"; resets = <&olb 0 11>; pinctrl-names = "default"; @@ -102,7 +120,7 @@ reg-io-width = <4>; interrupt-parent = <&gic>; interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_clk>, <&occ_periph>; + clocks = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>; clock-names = "uartclk", "apb_pclk"; resets = <&olb 0 12>; pinctrl-names = "default"; @@ -135,7 +153,7 @@ timer { compatible = "mti,gic-timer"; interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; - clocks = <&core0_clk>; + clocks = <&olb EQ5C_CPU_CORE0>; }; }; }; |