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| author | Paul Mackerras <paulus@ozlabs.org> | 2025-01-31 17:30:09 +1100 |
|---|---|---|
| committer | Madhavan Srinivasan <maddy@linux.ibm.com> | 2025-02-26 21:16:48 +0530 |
| commit | aca95fb6bb572a77f39d42d83ab72a965026577d (patch) | |
| tree | c87238f0c1ca4b1f4215171d49c691ed0076da50 /arch/powerpc/boot | |
| parent | 3d45a3d0d2e6b5cf47c6f0ab890f6ce762d9fd23 (diff) | |
| download | linux-aca95fb6bb572a77f39d42d83ab72a965026577d.tar.gz linux-aca95fb6bb572a77f39d42d83ab72a965026577d.tar.bz2 linux-aca95fb6bb572a77f39d42d83ab72a965026577d.zip | |
powerpc/microwatt: Add SMP support
This adds support for Microwatt systems with more than one core, and
updates the device tree for a 2-core version.
The secondary CPUs are started and sent to spin in __secondary_hold
very early on, in the platform probe function. The reason for doing
this is so that they are there when smp_release_cpus() gets called,
which is before the platform init_smp function or even the platform
setup_arch function gets called.
Note that having two CPUs in the device tree doesn't preclude
operation with only one CPU. The SYSCON_CPU_CTRL register has a
read-only field which indicates the number of CPU cores, so
microwatt_init_smp() will only start as many CPU cores as are present
in the system, and any extra CPU device-tree nodes will just be
ignored.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Link: https://patch.msgid.link/Z5xt8aooKyXZv6Kf@thinks.paulus.ozlabs.org
Diffstat (limited to 'arch/powerpc/boot')
| -rw-r--r-- | arch/powerpc/boot/dts/microwatt.dts | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts index 833d22822189..c4e4d2a9b460 100644 --- a/arch/powerpc/boot/dts/microwatt.dts +++ b/arch/powerpc/boot/dts/microwatt.dts @@ -142,6 +142,36 @@ ibm,mmu-lpid-bits = <12>; ibm,mmu-pid-bits = <20>; }; + + PowerPC,Microwatt@1 { + i-cache-sets = <2>; + ibm,dec-bits = <64>; + reservation-granule-size = <64>; + clock-frequency = <100000000>; + timebase-frequency = <100000000>; + i-tlb-sets = <1>; + ibm,ppc-interrupt-server#s = <1>; + i-cache-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <2>; + i-tlb-size = <64>; + cpu-version = <0x990000>; + status = "okay"; + i-cache-size = <0x1000>; + ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>; + tlb-size = <0>; + tlb-sets = <0>; + device_type = "cpu"; + d-tlb-size = <128>; + d-tlb-sets = <2>; + reg = <1>; + general-purpose; + 64-bit; + d-cache-size = <0x1000>; + ibm,chip-id = <0>; + ibm,mmu-lpid-bits = <12>; + ibm,mmu-pid-bits = <20>; + }; }; soc@c0000000 { @@ -154,8 +184,8 @@ interrupt-controller@4000 { compatible = "openpower,xics-presentation", "ibm,ppc-xicp"; - ibm,interrupt-server-ranges = <0x0 0x1>; - reg = <0x4000 0x100>; + ibm,interrupt-server-ranges = <0x0 0x2>; + reg = <0x4000 0x10 0x4010 0x10>; }; ICS: interrupt-controller@5000 { |