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| author | Thomas Gleixner <tglx@linutronix.de> | 2023-08-14 10:18:30 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2023-10-10 14:38:17 +0200 |
| commit | 02fb601d27a7abf60d52b21bdf5b100a8d63da3f (patch) | |
| tree | 63cb2e0fa0a7eaaa45a9164edad09ae5d467bcc2 /arch/x86/kernel/cpu/cacheinfo.c | |
| parent | b9655e702dc5d856e5e05ae414b71708ca98b30c (diff) | |
| download | linux-02fb601d27a7abf60d52b21bdf5b100a8d63da3f.tar.gz linux-02fb601d27a7abf60d52b21bdf5b100a8d63da3f.tar.bz2 linux-02fb601d27a7abf60d52b21bdf5b100a8d63da3f.zip | |
x86/cpu: Move phys_proc_id into topology info
Rename it to pkg_id which is the terminology used in the kernel.
No functional change.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Juergen Gross <jgross@suse.com>
Tested-by: Sohil Mehta <sohil.mehta@intel.com>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Zhang Rui <rui.zhang@intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230814085112.329006989@linutronix.de
Diffstat (limited to 'arch/x86/kernel/cpu/cacheinfo.c')
| -rw-r--r-- | arch/x86/kernel/cpu/cacheinfo.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index daa3542b6020..fe583fd634f5 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -875,10 +875,10 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * turns means that the only possibility is SMT (as indicated in * cpuid1). Since cpuid2 doesn't specify shared caches, and we know * that SMT shares all caches, we can unconditionally set cpu_llc_id to - * c->phys_proc_id. + * c->topo.pkg_id. */ if (per_cpu(cpu_llc_id, cpu) == BAD_APICID) - per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; + per_cpu(cpu_llc_id, cpu) = c->topo.pkg_id; #endif c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d)); |