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| author | James Morse <james.morse@arm.com> | 2022-09-02 15:48:16 +0000 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-09-22 17:17:59 +0200 |
| commit | 781096d971dfe3c5f9401a300bdb0b148a600584 (patch) | |
| tree | 56c9f9c2e0bffe7d1551ffddb81e9388874d6060 /arch/x86/kernel/cpu/resctrl/internal.h | |
| parent | b045c215866393419fb960432ed6be69a0113ee1 (diff) | |
| download | linux-781096d971dfe3c5f9401a300bdb0b148a600584.tar.gz linux-781096d971dfe3c5f9401a300bdb0b148a600584.tar.bz2 linux-781096d971dfe3c5f9401a300bdb0b148a600584.zip | |
x86/resctrl: Create mba_sc configuration in the rdt_domain
To support resctrl's MBA software controller, the architecture must provide
a second configuration array to hold the mbps_val[] from user-space.
This complicates the interface between the architecture specific code and
the filesystem portions of resctrl that will move to /fs/, to allow
multiple architectures to support resctrl.
Make the filesystem parts of resctrl create an array for the mba_sc
values. The software controller can be changed to use this, allowing
the architecture code to only consider the values configured in hardware.
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Jamie Iles <quic_jiles@quicinc.com>
Reviewed-by: Shaopeng Tan <tan.shaopeng@fujitsu.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Tested-by: Xin Hao <xhao@linux.alibaba.com>
Tested-by: Shaopeng Tan <tan.shaopeng@fujitsu.com>
Tested-by: Cristian Marussi <cristian.marussi@arm.com>
Link: https://lore.kernel.org/r/20220902154829.30399-9-james.morse@arm.com
Diffstat (limited to 'arch/x86/kernel/cpu/resctrl/internal.h')
| -rw-r--r-- | arch/x86/kernel/cpu/resctrl/internal.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index e12b55f815bf..a7e2cbce29d5 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -36,7 +36,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MBA_MAX_MBPS U32_MAX #define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 |