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| author | Chunyan Zhang <zhangchunyan@iscas.ac.cn> | 2024-10-08 17:41:39 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-11-08 16:22:03 +0100 |
| commit | d592b2e9212f2c9bba5ebe7759ed826979dc585d (patch) | |
| tree | 37a3139a52b831ee5c2ec4e028d6f012abdf5bdf /arch | |
| parent | 170ad7e7a6621f167edcc0922d40c9d6f96e589e (diff) | |
| download | linux-d592b2e9212f2c9bba5ebe7759ed826979dc585d.tar.gz linux-d592b2e9212f2c9bba5ebe7759ed826979dc585d.tar.bz2 linux-d592b2e9212f2c9bba5ebe7759ed826979dc585d.zip | |
riscv: Remove duplicated GET_RM
[ Upstream commit 164f66de6bb6ef454893f193c898dc8f1da6d18b ]
The macro GET_RM defined twice in this file, one can be removed.
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20241008094141.549248-3-zhangchunyan@iscas.ac.cn
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/kernel/traps_misaligned.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index b246c3dc6993..d548d6992d98 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -131,8 +131,6 @@ #define REG_PTR(insn, pos, regs) \ (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)) -#define GET_RM(insn) (((insn) >> 12) & 7) - #define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs)) #define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs)) #define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs)) |