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| author | Tim Harvey <tharvey@gateworks.com> | 2021-07-27 09:10:59 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-09-18 13:43:51 +0200 |
| commit | 628b2989239a7d7873cc0982f29e69d17d86cad1 (patch) | |
| tree | 81ef2dde9e8b44d802b9e5585dfae204f764e045 /arch | |
| parent | 66e37b54a4935d95bc436b012161eb2644090226 (diff) | |
| download | linux-628b2989239a7d7873cc0982f29e69d17d86cad1.tar.gz linux-628b2989239a7d7873cc0982f29e69d17d86cad1.tar.bz2 linux-628b2989239a7d7873cc0982f29e69d17d86cad1.zip | |
arm64: dts: imx8mm-venice-gw71xx: fix USB OTG VBUS
[ Upstream commit bd306fdb4e60bcb1d7ea5431a74092803d3784a6 ]
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12
is the power-enable to the TPS25821 Source controller and power switch
responsible for monitoring the CC pins and enabling VBUS. Therefore
GPIO1_12 must always be enabled and the vbus output enable from the
IMX8MM can be ignored.
To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the
TPS25821 and change the regulator output to GPIO1_10 which is
unconnected.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 905b68a3daa5..8e4a0ce99790 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -46,7 +46,7 @@ pinctrl-0 = <&pinctrl_reg_usb1_en>; compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -156,7 +156,8 @@ pinctrl_reg_usb1_en: regusb1grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 >; }; |