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| author | Quanyang Wang <quanyang.wang@windriver.com> | 2025-09-02 09:56:18 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-11-13 15:36:49 -0500 |
| commit | d1f60799a170cecdab79ff41c80031ebd0f9107c (patch) | |
| tree | 19e707aa231a15a38960431f4bba128205ed37d3 /arch | |
| parent | 74986b07dc26eb82ed186c32af3f73c3550136df (diff) | |
| download | linux-d1f60799a170cecdab79ff41c80031ebd0f9107c.tar.gz linux-d1f60799a170cecdab79ff41c80031ebd0f9107c.tar.bz2 linux-d1f60799a170cecdab79ff41c80031ebd0f9107c.zip | |
arm64: zynqmp: Disable coresight by default
[ Upstream commit 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca ]
When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.
Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e11d282462bd..23d867c03263 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -550,6 +550,7 @@ reg = <0x0 0xfec10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu0>; + status = "disabled"; }; cpu1_debug: debug@fed10000 { @@ -557,6 +558,7 @@ reg = <0x0 0xfed10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu1>; + status = "disabled"; }; cpu2_debug: debug@fee10000 { @@ -564,6 +566,7 @@ reg = <0x0 0xfee10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu2>; + status = "disabled"; }; cpu3_debug: debug@fef10000 { @@ -571,6 +574,7 @@ reg = <0x0 0xfef10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu3>; + status = "disabled"; }; /* GDMA */ |