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| author | Guillaume La Roque <glaroque@baylibre.com> | 2025-11-23 18:14:10 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-12-18 14:03:19 +0100 |
| commit | 46cd9849e5207e92b2f1d429a4688d4954c5918b (patch) | |
| tree | 5cf7b01ee01cc5f498c390bde6cad51f48c40226 /arch | |
| parent | 73573f7e52842dfb1c205a6617afe5ae49335ea0 (diff) | |
| download | linux-46cd9849e5207e92b2f1d429a4688d4954c5918b.tar.gz linux-46cd9849e5207e92b2f1d429a4688d4954c5918b.tar.bz2 linux-46cd9849e5207e92b2f1d429a4688d4954c5918b.zip | |
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
[ Upstream commit a7ab6f946683e065fa22db1cc2f2748d4584178a ]
The original addition of cache information for the Amlogic S922X SoC
used the wrong next-level cache node for CPU cores 100 and 101,
incorrectly referencing `l2_cache_l`. These cores actually belong to
the big cluster and should reference `l2_cache_b`. Update the device
tree accordingly.
Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251123-fixkhadas-v1-1-045348f0a4c2@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index f04efa828256..23358d94844c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -87,7 +87,7 @@ i-cache-line-size = <32>; i-cache-size = <0x8000>; i-cache-sets = <32>; - next-level-cache = <&l2_cache_l>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; @@ -103,7 +103,7 @@ i-cache-line-size = <32>; i-cache-size = <0x8000>; i-cache-sets = <32>; - next-level-cache = <&l2_cache_l>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; |