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| author | Huacai Chen <chenhuacai@loongson.cn> | 2025-11-20 14:42:05 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-12-01 11:41:43 +0100 |
| commit | fe694895d3b7d391130bb505220383ab0b70e7b4 (patch) | |
| tree | 8c1102d16c7e5bd434074fc2a06d9edb79c35b4a /arch | |
| parent | 6aa22377ef273193fdbb5b31ef358c49a7e3aeb4 (diff) | |
| download | linux-fe694895d3b7d391130bb505220383ab0b70e7b4.tar.gz linux-fe694895d3b7d391130bb505220383ab0b70e7b4.tar.bz2 linux-fe694895d3b7d391130bb505220383ab0b70e7b4.zip | |
LoongArch: Don't panic if no valid cache info for PCI
commit a6b533adfc05ba15360631e019d3e18275080275 upstream.
If there is no valid cache info detected (may happen in virtual machine)
for pci_dfl_cache_line_size, kernel shouldn't panic. Because in the PCI
core it will be evaluated to (L1_CACHE_BYTES >> 2).
Cc: <stable@vger.kernel.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/loongarch/pci/pci.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/loongarch/pci/pci.c b/arch/loongarch/pci/pci.c index 2726639150bc..927dd31f82b9 100644 --- a/arch/loongarch/pci/pci.c +++ b/arch/loongarch/pci/pci.c @@ -51,11 +51,11 @@ static int __init pcibios_init(void) */ lsize = cpu_last_level_cache_line_size(); - BUG_ON(!lsize); + if (lsize) { + pci_dfl_cache_line_size = lsize >> 2; - pci_dfl_cache_line_size = lsize >> 2; - - pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); + pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize); + } return 0; } |